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wdenk4e7a58a2003-12-07 19:24:00 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28#define MV_VERSION "v0.2.0"
29
30/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
Wolfgang Denka1be4762008-05-20 16:00:29 +020031#define ERR_NONE 0
32#define ERR_ENV 1
33#define ERR_BOOTM_BADMAGIC 2
34#define ERR_BOOTM_BADCRC 3
35#define ERR_BOOTM_GUNZIP 4
wdenk4e7a58a2003-12-07 19:24:00 +000036#define ERR_BOOTP_TIMEOUT 5
Wolfgang Denka1be4762008-05-20 16:00:29 +020037#define ERR_DHCP 6
38#define ERR_TFTP 7
39#define ERR_NOLAN 8
40#define ERR_LANDRV 9
wdenk4e7a58a2003-12-07 19:24:00 +000041
42#define CONFIG_BOARD_TYPES 1
43#define MVBLUE_BOARD_BOX 1
44#define MVBLUE_BOARD_LYNX 2
45
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Wolfgang Denk79362d32010-11-23 23:48:56 +010047#define CONFIG_SYS_LDSCRIPT "board/mvblue/u-boot.lds"
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020048
wdenk4e7a58a2003-12-07 19:24:00 +000049#if 0
50#define ERR_LED(code) do { if (code) \
Wolfgang Denka1be4762008-05-20 16:00:29 +020051 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
52 else \
53 *(volatile char *)(0xff000003) = ( 1 ); \
54} while(0)
wdenk4e7a58a2003-12-07 19:24:00 +000055#else
56#define ERR_LED(code)
57#endif
58
wdenk4e7a58a2003-12-07 19:24:00 +000059#define CONFIG_MPC824X 1
60#define CONFIG_MPC8245 1
61#define CONFIG_MVBLUE 1
62
63#define CONFIG_CLOCKS_IN_MHZ 1
64
Stefan Roese37628252008-08-06 14:05:38 +020065#define CONFIG_BOARD_TYPES 1
wdenk4e7a58a2003-12-07 19:24:00 +000066
67#define CONFIG_CONS_INDEX 1
68#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk4e7a58a2003-12-07 19:24:00 +000070
Stefan Roese37628252008-08-06 14:05:38 +020071#define CONFIG_BOOTDELAY 3
wdenk4e7a58a2003-12-07 19:24:00 +000072#define CONFIG_BOOT_RETRY_TIME -1
73
74#define CONFIG_AUTOBOOT_KEYED
Stefan Roese37628252008-08-06 14:05:38 +020075#define CONFIG_AUTOBOOT_PROMPT \
76 "autoboot in %d seconds (stop with 's')...\n", bootdelay
wdenk1ebf41e2004-01-02 14:00:00 +000077#define CONFIG_AUTOBOOT_STOP_STR "s"
wdenk4e7a58a2003-12-07 19:24:00 +000078#define CONFIG_ZERO_BOOTDELAY_CHECK
79#define CONFIG_RESET_TO_RETRY 60
80
wdenk4e7a58a2003-12-07 19:24:00 +000081
Jon Loeliger446e1f52007-07-08 14:14:17 -050082/*
83 * Command line configuration.
84 */
wdenk4e7a58a2003-12-07 19:24:00 +000085
Jon Loeliger446e1f52007-07-08 14:14:17 -050086#define CONFIG_CMD_ASKENV
87#define CONFIG_CMD_BOOTD
88#define CONFIG_CMD_CACHE
89#define CONFIG_CMD_DHCP
90#define CONFIG_CMD_ECHO
Mike Frysinger78dcaf42009-01-28 19:08:14 -050091#define CONFIG_CMD_SAVEENV
Jon Loeliger446e1f52007-07-08 14:14:17 -050092#define CONFIG_CMD_FLASH
93#define CONFIG_CMD_IMI
Jon Loeliger446e1f52007-07-08 14:14:17 -050094#define CONFIG_CMD_NET
95#define CONFIG_CMD_PCI
96#define CONFIG_CMD_RUN
wdenk4e7a58a2003-12-07 19:24:00 +000097
Jon Loeliger446e1f52007-07-08 14:14:17 -050098
Jon Loeligerdf5f5442007-07-09 21:24:19 -050099/*
100 * BOOTP options
101 */
102#define CONFIG_BOOTP_SUBNETMASK
103#define CONFIG_BOOTP_GATEWAY
104#define CONFIG_BOOTP_HOSTNAME
105#define CONFIG_BOOTP_BOOTPATH
106#define CONFIG_BOOTP_BOOTFILESIZE
107#define CONFIG_BOOTP_SUBNETMASK
108#define CONFIG_BOOTP_GATEWAY
109#define CONFIG_BOOTP_HOSTNAME
110#define CONFIG_BOOTP_NISDOMAIN
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_DNS
113#define CONFIG_BOOTP_DNS2
114#define CONFIG_BOOTP_SEND_HOSTNAME
115#define CONFIG_BOOTP_NTPSERVER
116#define CONFIG_BOOTP_TIMEOFFSET
117
wdenk4e7a58a2003-12-07 19:24:00 +0000118
119/*
120 * Miscellaneous configurable options
121 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_LONGHELP /* undef to save memory */
123#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
124#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk4e7a58a2003-12-07 19:24:00 +0000125
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
127#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenk4e7a58a2003-12-07 19:24:00 +0000130
Wolfgang Denka1be4762008-05-20 16:00:29 +0200131#define CONFIG_BOOTCOMMAND "run nfsboot"
wdenk4e7a58a2003-12-07 19:24:00 +0000132#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
133
Wolfgang Denka1be4762008-05-20 16:00:29 +0200134#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
wdenk4e7a58a2003-12-07 19:24:00 +0000135
wdenk1ebf41e2004-01-02 14:00:00 +0000136#define CONFIG_EXTRA_ENV_SETTINGS \
137 "console_nr=0\0" \
138 "dhcp_client_id=mvBOX-XP\0" \
139 "dhcp_vendor-class-identifier=mvBOX\0" \
140 "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
141 "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
142 "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
143 "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
Wolfgang Denk86eb3b72005-11-20 21:40:11 +0100144 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
145 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
146 "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
wdenk4e7a58a2003-12-07 19:24:00 +0000147 "mv_version=" MV_VERSION "\0" \
wdenk1ebf41e2004-01-02 14:00:00 +0000148 "bootretry=30\0"
wdenk4e7a58a2003-12-07 19:24:00 +0000149
150#define CONFIG_OVERWRITE_ETHADDR_ONCE
151
152/*-----------------------------------------------------------------------
153 * PCI stuff
154 *-----------------------------------------------------------------------
155 */
156
wdenk1ebf41e2004-01-02 14:00:00 +0000157#define CONFIG_PCI
wdenk4e7a58a2003-12-07 19:24:00 +0000158#define CONFIG_PCI_PNP
159#define CONFIG_PCI_SCAN_SHOW
160
wdenk1ebf41e2004-01-02 14:00:00 +0000161#define CONFIG_NET_MULTI
Wolfgang Denka1be4762008-05-20 16:00:29 +0200162#define CONFIG_NET_RETRY_COUNT 5
wdenk4e7a58a2003-12-07 19:24:00 +0000163
164#define CONFIG_TULIP
165#define CONFIG_TULIP_FIX_DAVICOM 1
Wolfgang Denka1be4762008-05-20 16:00:29 +0200166#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
wdenk4e7a58a2003-12-07 19:24:00 +0000167
168#define CONFIG_HW_WATCHDOG
169
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk4e7a58a2003-12-07 19:24:00 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk4e7a58a2003-12-07 19:24:00 +0000176
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_BASE 0xFFF00000
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk4e7a58a2003-12-07 19:24:00 +0000179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
181#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenk4e7a58a2003-12-07 19:24:00 +0000182
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_MONITOR_LEN 0x00100000
184#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
wdenk4e7a58a2003-12-07 19:24:00 +0000185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
187#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
wdenk4e7a58a2003-12-07 19:24:00 +0000188
189/* Maximum amount of RAM. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
wdenk4e7a58a2003-12-07 19:24:00 +0000191
192
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
194#undef CONFIG_SYS_RAMBOOT
wdenk4e7a58a2003-12-07 19:24:00 +0000195#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200196#define CONFIG_SYS_RAMBOOT
wdenk4e7a58a2003-12-07 19:24:00 +0000197#endif
198
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_ISA_IO 0xFE000000
wdenk4e7a58a2003-12-07 19:24:00 +0000200
201/*
202 * serial configuration
203 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204#define CONFIG_SYS_NS16550
205#define CONFIG_SYS_NS16550_SERIAL
wdenk4e7a58a2003-12-07 19:24:00 +0000206
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk4e7a58a2003-12-07 19:24:00 +0000208
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk4e7a58a2003-12-07 19:24:00 +0000210
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200211#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
212#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenk4e7a58a2003-12-07 19:24:00 +0000213
214/*-----------------------------------------------------------------------
215 * Definitions for initial stack pointer and data area
216 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200218#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk0191e472010-10-26 14:34:52 +0200219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk4e7a58a2003-12-07 19:24:00 +0000220
221/*
222 * Low Level Configuration Settings
223 * (address mappings, register initial values, etc.)
224 * You should know what you are doing if you make changes here.
225 * For the detail description refer to the MPC8240 user's manual.
226 */
227
wdenk1ebf41e2004-01-02 14:00:00 +0000228#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200229#define CONFIG_SYS_HZ 10000
wdenk4e7a58a2003-12-07 19:24:00 +0000230
231/* Bit-field values for MCCR1. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200232#define CONFIG_SYS_ROMNAL 7
233#define CONFIG_SYS_ROMFAL 11
wdenk4e7a58a2003-12-07 19:24:00 +0000234
235/* Bit-field values for MCCR2. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200236#define CONFIG_SYS_TSWAIT 0x5
237#define CONFIG_SYS_REFINT 430
wdenk4e7a58a2003-12-07 19:24:00 +0000238
239/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240#define CONFIG_SYS_BSTOPRE 121
wdenk4e7a58a2003-12-07 19:24:00 +0000241
242/* Bit-field values for MCCR3. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#define CONFIG_SYS_REFREC 8
wdenk4e7a58a2003-12-07 19:24:00 +0000244
245/* Bit-field values for MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200246#define CONFIG_SYS_PRETOACT 3
247#define CONFIG_SYS_ACTTOPRE 5
248#define CONFIG_SYS_ACTORW 3
249#define CONFIG_SYS_SDMODE_CAS_LAT 3
250#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
251#define CONFIG_SYS_EXTROM 1
252#define CONFIG_SYS_REGDIMM 0
253#define CONFIG_SYS_DBUS_SIZE2 1
254#define CONFIG_SYS_SDMODE_WRAP 0
wdenk4e7a58a2003-12-07 19:24:00 +0000255
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_PGMAX 0x32
257#define CONFIG_SYS_SDRAM_DSCD 0x20
wdenk4e7a58a2003-12-07 19:24:00 +0000258
259/* Memory bank settings.
260 * Only bits 20-29 are actually used from these vales to set the
261 * start/end addresses. The upper two bits will always be 0, and the lower
262 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
263 * address. Refer to the MPC8240 book.
264 */
265
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_BANK0_START 0x00000000
267#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
268#define CONFIG_SYS_BANK0_ENABLE 1
269#define CONFIG_SYS_BANK1_START 0x3ff00000
270#define CONFIG_SYS_BANK1_END 0x3fffffff
271#define CONFIG_SYS_BANK1_ENABLE 0
272#define CONFIG_SYS_BANK2_START 0x3ff00000
273#define CONFIG_SYS_BANK2_END 0x3fffffff
274#define CONFIG_SYS_BANK2_ENABLE 0
275#define CONFIG_SYS_BANK3_START 0x3ff00000
276#define CONFIG_SYS_BANK3_END 0x3fffffff
277#define CONFIG_SYS_BANK3_ENABLE 0
278#define CONFIG_SYS_BANK4_START 0x3ff00000
279#define CONFIG_SYS_BANK4_END 0x3fffffff
280#define CONFIG_SYS_BANK4_ENABLE 0
281#define CONFIG_SYS_BANK5_START 0x3ff00000
282#define CONFIG_SYS_BANK5_END 0x3fffffff
283#define CONFIG_SYS_BANK5_ENABLE 0
284#define CONFIG_SYS_BANK6_START 0x3ff00000
285#define CONFIG_SYS_BANK6_END 0x3fffffff
286#define CONFIG_SYS_BANK6_ENABLE 0
287#define CONFIG_SYS_BANK7_START 0x3ff00000
288#define CONFIG_SYS_BANK7_END 0x3fffffff
289#define CONFIG_SYS_BANK7_ENABLE 0
wdenk4e7a58a2003-12-07 19:24:00 +0000290
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#define CONFIG_SYS_ODCR 0xff
wdenk4e7a58a2003-12-07 19:24:00 +0000292
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200293#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
294#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk4e7a58a2003-12-07 19:24:00 +0000295
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200296#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
297#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk4e7a58a2003-12-07 19:24:00 +0000298
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
300#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk4e7a58a2003-12-07 19:24:00 +0000301
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200302#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
303#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk4e7a58a2003-12-07 19:24:00 +0000304
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200305#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
306#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
307#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
308#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
309#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
310#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
311#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
312#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk4e7a58a2003-12-07 19:24:00 +0000313
314/*
315 * For booting Linux, the board info and command line data
316 * have to be in the first 8 MB of memory, since this is
317 * the maximum mapped by the Linux kernel during initialization.
318 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200319#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk4e7a58a2003-12-07 19:24:00 +0000320
321/*-----------------------------------------------------------------------
322 * FLASH organization
323 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200324#undef CONFIG_SYS_FLASH_PROTECTION
325#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
326#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
wdenk4e7a58a2003-12-07 19:24:00 +0000327
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200328#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
329#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
wdenk4e7a58a2003-12-07 19:24:00 +0000330
331
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200332#define CONFIG_ENV_IS_IN_FLASH
wdenk4e7a58a2003-12-07 19:24:00 +0000333
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200334#define CONFIG_ENV_OFFSET 0x00010000
335#define CONFIG_ENV_SIZE 0x00010000
336#define CONFIG_ENV_SECT_SIZE 0x00010000
wdenk4e7a58a2003-12-07 19:24:00 +0000337
338/*-----------------------------------------------------------------------
339 * Cache Configuration
340 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger446e1f52007-07-08 14:14:17 -0500342#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200343#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk4e7a58a2003-12-07 19:24:00 +0000344#endif
wdenk4e7a58a2003-12-07 19:24:00 +0000345#endif /* __CONFIG_H */