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git01.mediatek.com / filogic / uboot / e828edd1dcdeb2bed5aef8c515f376ddd23bbdae / . / arch / riscv / dts / microchip-mpfs-icicle-kit.dts
blob: c3f58e2d56fe0e0246311be9d5ca1d9a94e418dc [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]3 * Copyright (C) 2021-2022 Microchip Technology Inc.
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]6
7/dts-v1/;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]8
9#include "microchip-mpfs.dtsi"
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ 1000000
13
14/ {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]15 model = "Microchip PolarFire-SoC Icicle Kit";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]16 compatible = "microchip,mpfs-icicle-reference-rtlv2210",
17 "microchip,mpfs-icicle-kit", "microchip,mpfs";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]18
19 aliases {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]20 serial1 = &uart1;
21 ethernet0 = &mac1;
Padmarao Begarida2a6d02022-10-27 11:32:00 +0530[diff] [blame]22 spi0 = &qspi;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]23 };
24
25 chosen {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]26 stdout-path = "serial1";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]27 };
28
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]29 cpus {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]30 timebase-frequency = <RTCCLK_FREQ>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]31 };
32
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]33 ddrc_cache_lo: memory@80000000 {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]34 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]35 reg = <0x0 0x80000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]36 status = "okay";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]37 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]38
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]39 ddrc_cache_hi: memory@1040000000 {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]40 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]41 reg = <0x10 0x40000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]42 status = "okay";
43 };
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame]44
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 hss_payload: region@BFC00000 {
51 reg = <0x0 0xBFC00000 0x0 0x400000>;
52 no-map;
53 };
54 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]55};
56
Conor Dooleye828edd2022-10-25 08:58:49 +0100[diff] [blame^]57&refclk {
58 clock-frequency = <125000000>;
59};
60
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]61&uart1 {
62 status = "okay";
63};
64
65&mmc {
66 status = "okay";
67
68 bus-width = <4>;
69 disable-wp;
70 cap-mmc-highspeed;
71 cap-sd-highspeed;
72 card-detect-delay = <200>;
73 mmc-ddr-1_8v;
74 mmc-hs200-1_8v;
75 sd-uhs-sdr12;
76 sd-uhs-sdr25;
77 sd-uhs-sdr50;
78 sd-uhs-sdr104;
79};
80
81&i2c1 {
82 status = "okay";
83 clock-frequency = <100000>;
84
85 pac193x: pac193x@10 {
86 compatible = "microchip,pac1934";
87 reg = <0x10>;
88 samp-rate = <64>;
89 status = "okay";
90 ch1: channel0 {
91 uohms-shunt-res = <10000>;
92 rail-name = "VDDREG";
93 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]94 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]95 ch2: channel1 {
96 uohms-shunt-res = <10000>;
97 rail-name = "VDDA25";
98 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]99 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]100 ch3: channel2 {
101 uohms-shunt-res = <10000>;
102 rail-name = "VDD25";
103 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]104 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]105 ch4: channel3 {
106 uohms-shunt-res = <10000>;
107 rail-name = "VDDA_REG";
108 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]109 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]110 };
111};
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]112
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]113&mac1 {
114 status = "okay";
115 phy-mode = "sgmii";
116 phy-handle = <&phy1>;
117 phy1: ethernet-phy@9 {
118 reg = <9>;
119 ti,fifo-depth = <0x1>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]120 };
121};
Padmarao Begarida2a6d02022-10-27 11:32:00 +0530[diff] [blame]122
123&qspi {
124 status = "okay";
125 num-cs = <1>;
126
127 flash0: flash@0 {
128 compatible = "spi-nand";
129 reg = <0x0>;
130 spi-tx-bus-width = <4>;
131 spi-rx-bus-width = <4>;
132 spi-max-frequency = <20000000>;
133 spi-cpol;
134 spi-cpha;
135 };
136};