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git01.mediatek.com / filogic / uboot / c66a3b2d7c7a3171d3122fb379c01e904358751d / . / arch / riscv / dts / microchip-mpfs-icicle-kit.dts
blob: 48fc2bf06ad043684364dbf78ba856878fc48ef6 [file] [log] [blame]
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]3 * Copyright (C) 2021-2022 Microchip Technology Inc.
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]6
7/dts-v1/;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]8
9#include "microchip-mpfs.dtsi"
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]10
11/* Clock frequency (in Hz) of the rtcclk */
12#define RTCCLK_FREQ 1000000
13
14/ {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]15 model = "Microchip PolarFire-SoC Icicle Kit";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]16 compatible = "microchip,mpfs-icicle-reference-rtlv2210",
17 "microchip,mpfs-icicle-kit", "microchip,mpfs";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]18
19 aliases {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]20 serial1 = &uart1;
21 ethernet0 = &mac1;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]22 };
23
24 chosen {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]25 stdout-path = "serial1";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]26 };
27
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]28 cpus {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]29 timebase-frequency = <RTCCLK_FREQ>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]30 };
31
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]32 ddrc_cache_lo: memory@80000000 {
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]33 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]34 reg = <0x0 0x80000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]35 status = "okay";
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]36 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]37
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]38 ddrc_cache_hi: memory@1040000000 {
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]39 device_type = "memory";
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]40 reg = <0x10 0x40000000 0x0 0x40000000>;
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]41 status = "okay";
42 };
Padmarao Begaric66a3b22022-10-27 11:31:59 +0530[diff] [blame^]43
44 reserved-memory {
45 #address-cells = <2>;
46 #size-cells = <2>;
47 ranges;
48
49 hss_payload: region@BFC00000 {
50 reg = <0x0 0xBFC00000 0x0 0x400000>;
51 no-map;
52 };
53 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]54};
55
56&uart1 {
57 status = "okay";
58};
59
60&mmc {
61 status = "okay";
62
63 bus-width = <4>;
64 disable-wp;
65 cap-mmc-highspeed;
66 cap-sd-highspeed;
67 card-detect-delay = <200>;
68 mmc-ddr-1_8v;
69 mmc-hs200-1_8v;
70 sd-uhs-sdr12;
71 sd-uhs-sdr25;
72 sd-uhs-sdr50;
73 sd-uhs-sdr104;
74};
75
76&i2c1 {
77 status = "okay";
78 clock-frequency = <100000>;
79
80 pac193x: pac193x@10 {
81 compatible = "microchip,pac1934";
82 reg = <0x10>;
83 samp-rate = <64>;
84 status = "okay";
85 ch1: channel0 {
86 uohms-shunt-res = <10000>;
87 rail-name = "VDDREG";
88 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]89 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]90 ch2: channel1 {
91 uohms-shunt-res = <10000>;
92 rail-name = "VDDA25";
93 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]94 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]95 ch3: channel2 {
96 uohms-shunt-res = <10000>;
97 rail-name = "VDD25";
98 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]99 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]100 ch4: channel3 {
101 uohms-shunt-res = <10000>;
102 rail-name = "VDDA_REG";
103 channel_enabled;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]104 };
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]105 };
106};
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]107
Padmarao Begarib56e2fd2021-11-17 18:21:17 +0530[diff] [blame]108&mac1 {
109 status = "okay";
110 phy-mode = "sgmii";
111 phy-handle = <&phy1>;
112 phy1: ethernet-phy@9 {
113 reg = <9>;
114 ti,fifo-depth = <0x1>;
Padmarao Begari5854c3d2021-01-15 08:20:39 +0530[diff] [blame]115 };
116};