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git01.mediatek.com / filogic / uboot / e735b681399495cfacd240e451c6414f9be6e306 / . / board / amcc / yucca / init.S
blob: 7da5c0d44fb4467419c7de92dd90dec782a2706f [file] [log] [blame]
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]1/*
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]8 */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]9
10#include <ppc_asm.tmpl>
11#include <config.h>
Peter Tyser133c0fe2010-04-12 22:28:07 -0500[diff] [blame]12#include <asm/mmu.h>
Stefan Roese3ddce572010-09-20 16:05:31 +0200[diff] [blame]13#include <asm/ppc4xx.h>
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]14
15/**************************************************************************
16 * TLB TABLE
17 *
18 * This table is used by the cpu boot code to setup the initial tlb
19 * entries. Rather than make broad assumptions in the cpu source tree,
20 * this table lets each board set things up however they like.
21 *
22 * Pointer to the table is returned in r1
23 *
24 *************************************************************************/
25
26 .section .bootpg,"ax"
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]27
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]28/**************************************************************************
29 * TLB table for revA
30 *************************************************************************/
31 .globl tlbtabA
32tlbtabA:
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]33 tlbtab_start
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]34
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]35 /*
36 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
37 * speed up boot process. It is patched after relocation to enable SA_I
38 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]39 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]40
41 /*
42 * TLB entries for SDRAM are not needed on this platform.
43 * They are dynamically generated in the SPD DDR(2) detection
44 * routine.
45 */
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]46
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]47 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
48 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]49
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]50 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
51 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]52
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]53 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
54 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
55 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
56 tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]57
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]58 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
59 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
60 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
61 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
62 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
63 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]64 tlbtab_end
65
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]66/**************************************************************************
67 * TLB table for revB
68 *
Wolfgang Denkb8474132006-08-10 15:40:49 +0200[diff] [blame]69 * Notice: revB of the 440SPe chip is very strict about PLB real addresses
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]70 * and ranges to be mapped for config space: it seems to only work with
71 * d_nnnn_nnnn range (hangs the core upon config transaction attempts when
72 * set otherwise) while revA uses c_nnnn_nnnn.
73 *************************************************************************/
74 .globl tlbtabB
75tlbtabB:
76 tlbtab_start
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]77
78 /*
79 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
80 * speed up boot process. It is patched after relocation to enable SA_I
81 */
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]82 tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]83
Stefan Roese511b61d2007-03-08 10:10:18 +0100[diff] [blame]84 /*
85 * TLB entries for SDRAM are not needed on this platform.
86 * They are dynamically generated in the SPD DDR(2) detection
87 * routine.
88 */
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]89
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]90 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
91 tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]92
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]93 tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
94 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]95
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]96 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
97 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
98 tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Rafal Jaworowskia2e7ef02006-08-10 12:43:17 +0200[diff] [blame]99
Stefan Roese94b62702010-04-14 13:57:18 +0200[diff] [blame]100 tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
101 tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
102 tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
103 tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
104 tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
105 tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
Marian Balakowicz49d0eee2006-06-30 16:30:46 +0200[diff] [blame]106 tlbtab_end