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git01.mediatek.com / filogic / uboot / e722852ecc15d5e57cbe520194a3e12656b7f6e0 / . / board / sbc8548 / law.c
blob: e1f90a06f850391fcce291c850641377f44dfd8b [file] [log] [blame]
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0+
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]8 */
9
10#include <common.h>
11#include <asm/fsl_law.h>
12#include <asm/mmu.h>
13
14/*
15 * LAW(Local Access Window) configuration:
16 *
17 * 0x0000_0000 0x0fff_ffff DDR 256M
18 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]19 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]20 * 0xe000_0000 0xe000_ffff CCSR 1M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]21 * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
22 * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]23 * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]24 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
25 * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]26 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
27 *
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]28 * If swapped CS0/CS6 via JP12+SW2.8:
29 * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
30 * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
31 *
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]32 * Notes:
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]33 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]34 * If flash is 8M at default position (last 8M), no LAW needed.
35 */
36
37struct law_entry law_table[] = {
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]38#ifdef CONFIG_SYS_ALT_BOOT
39 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
40#else
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]41 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]42#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]43#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]44 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]45#endif
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame]46#ifdef CONFIG_SYS_LBC_SDRAM_BASE
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]47 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]48 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame]49#else
50 /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
51 SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
52#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]53};
54
55int num_law_entries = ARRAY_SIZE(law_table);