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git01.mediatek.com / filogic / uboot / 17f9184efe33f810edd849ef2d06eb0d84efe933 / . / board / sbc8548 / law.c
blob: 322af76d659ece2878588f9abbd873aca74babf1 [file] [log] [blame]
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/fsl_law.h>
28#include <asm/mmu.h>
29
30/*
31 * LAW(Local Access Window) configuration:
32 *
33 * 0x0000_0000 0x0fff_ffff DDR 256M
34 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]35 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]36 * 0xe000_0000 0xe000_ffff CCSR 1M
Paul Gortmaker3bff6422009-09-20 20:36:05 -0400[diff] [blame]37 * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
38 * 0xe280_0000 0xe2ff_ffff PCIe IO 8M
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]39 * 0xec00_0000 0xefff_ffff FLASH (2nd bank) 64M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]40 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
41 * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]42 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
43 *
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]44 * If swapped CS0/CS6 via JP12+SW2.8:
45 * 0xef80_0000 0xefff_ffff FLASH (2nd bank) 8M
46 * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
47 *
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]48 * Notes:
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]49 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]50 * If flash is 8M at default position (last 8M), no LAW needed.
51 */
52
53struct law_entry law_table[] = {
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]54#ifdef CONFIG_SYS_ALT_BOOT
55 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
56#else
Paul Gortmakera6d378a2011-12-30 23:53:07 -0500[diff] [blame]57 SET_LAW(CONFIG_SYS_ALT_FLASH, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
Paul Gortmaker626fa262011-12-30 23:53:08 -0500[diff] [blame]58#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]59#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]60 SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]61#endif
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame^]62#ifdef CONFIG_SYS_LBC_SDRAM_BASE
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]63 /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]64 SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
Paul Gortmaker17f91842011-12-30 23:53:10 -0500[diff] [blame^]65#else
66 /* LBC window - maps 128M 0xf8000000 -> 0xffffffff */
67 SET_LAW(CONFIG_SYS_EPLD_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
68#endif
Kumar Galab2343422008-01-16 09:05:27 -0600[diff] [blame]69};
70
71int num_law_entries = ARRAY_SIZE(law_table);