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Mike Rapoport8abe7302010-12-18 17:43:19 -05001/*
Nikita Kiryanov0630b032012-01-02 04:01:30 +00002 * (C) Copyright 2011 CompuLab, Ltd.
Mike Rapoport8abe7302010-12-18 17:43:19 -05003 * Mike Rapoport <mike@compulab.co.il>
Igor Grinbergbebedbf2011-04-18 17:48:31 -04004 * Igor Grinberg <grinberg@compulab.co.il>
Mike Rapoport8abe7302010-12-18 17:43:19 -05005 *
6 * Based on omap3_beagle.h
7 * (C) Copyright 2006-2008
8 * Texas Instruments.
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <x0khasim@ti.com>
11 *
Igor Grinberg05a96a42011-04-18 17:55:21 -040012 * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
Mike Rapoport8abe7302010-12-18 17:43:19 -050013 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Mike Rapoport8abe7302010-12-18 17:43:19 -050015 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
Albert ARIBAUDbf9032a2016-01-27 08:46:11 +010020#define CONFIG_SYS_CACHELINE_SIZE 64
21
Mike Rapoport8abe7302010-12-18 17:43:19 -050022/*
23 * High Level Configuration Options
24 */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000025#define CONFIG_OMAP /* in a TI OMAP core */
Marek Vasutaede1882012-07-21 05:02:23 +000026#define CONFIG_OMAP_GPIO
Nikita Kiryanov0630b032012-01-02 04:01:30 +000027#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
Lokesh Vutla56055052013-07-30 11:36:30 +053028#define CONFIG_OMAP_COMMON
Nishanth Menon3e46e3e2015-03-09 17:12:08 -050029/* Common ARM Erratas */
30#define CONFIG_ARM_ERRATA_454179
31#define CONFIG_ARM_ERRATA_430973
32#define CONFIG_ARM_ERRATA_621766
Mike Rapoport8abe7302010-12-18 17:43:19 -050033
Mike Rapoport8abe7302010-12-18 17:43:19 -050034#define CONFIG_SDRC /* The chip has SDRC controller */
35
36#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menonfa96c962015-03-09 17:12:04 -050037#include <asm/arch/omap.h>
Mike Rapoport8abe7302010-12-18 17:43:19 -050038
Mike Rapoport8abe7302010-12-18 17:43:19 -050039/* Clock Defines */
40#define V_OSCK 26000000 /* Clock output from T2 */
41#define V_SCLK (V_OSCK >> 1)
42
Mike Rapoport8abe7302010-12-18 17:43:19 -050043#define CONFIG_MISC_INIT_R
44
Nikita Kiryanov0630b032012-01-02 04:01:30 +000045#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
46#define CONFIG_SETUP_MEMORY_TAGS
47#define CONFIG_INITRD_TAG
48#define CONFIG_REVISION_TAG
Nikita Kiryanovb47cb9d2012-01-12 03:26:30 +000049#define CONFIG_SERIAL_TAG
Mike Rapoport8abe7302010-12-18 17:43:19 -050050
51/*
52 * Size of malloc() pool
53 */
Igor Grinbergf497f7f2012-05-24 04:01:21 +000054#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000055 /* Sector */
56#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Mike Rapoport8abe7302010-12-18 17:43:19 -050057
58/*
59 * Hardware drivers
60 */
61
62/*
63 * NS16550 Configuration
64 */
65#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
66
Mike Rapoport8abe7302010-12-18 17:43:19 -050067#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE (-4)
69#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70
71/*
72 * select serial console configuration
73 */
74#define CONFIG_CONS_INDEX 3
75#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
76#define CONFIG_SERIAL3 3 /* UART3 */
77
78/* allow to overwrite serial and ethaddr */
79#define CONFIG_ENV_OVERWRITE
80#define CONFIG_BAUDRATE 115200
81#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 115200}
Nikita Kiryanov0630b032012-01-02 04:01:30 +000083
84#define CONFIG_GENERIC_MMC
85#define CONFIG_MMC
86#define CONFIG_OMAP_HSMMC
87#define CONFIG_DOS_PARTITION
Mike Rapoport8abe7302010-12-18 17:43:19 -050088
Mike Rapoport8abe7302010-12-18 17:43:19 -050089/* USB */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000090#define CONFIG_USB_OMAP3
Nikita Kiryanov9f957be2012-12-02 13:59:19 +020091#define CONFIG_USB_EHCI
92#define CONFIG_USB_EHCI_OMAP
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +020093#define CONFIG_USB_MUSB_UDC
Nikita Kiryanov0630b032012-01-02 04:01:30 +000094#define CONFIG_TWL4030_USB
Mike Rapoport8abe7302010-12-18 17:43:19 -050095
96/* USB device configuration */
Nikita Kiryanov0630b032012-01-02 04:01:30 +000097#define CONFIG_USB_DEVICE
98#define CONFIG_USB_TTY
99#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Mike Rapoport8abe7302010-12-18 17:43:19 -0500100
101/* commands to include */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500102#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
103#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
Igor Grinberg23964602013-04-22 01:06:55 +0000104#define CONFIG_MTD_PARTITIONS
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000105#define MTDIDS_DEFAULT "nand0=nand"
106#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
Igor Grinberg23964602013-04-22 01:06:55 +0000107 "1920k(u-boot),256k(u-boot-env),"\
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000108 "4m(kernel),-(fs)"
Mike Rapoport8abe7302010-12-18 17:43:19 -0500109
Mike Rapoport8abe7302010-12-18 17:43:19 -0500110#define CONFIG_CMD_NAND /* NAND support */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500111
Mike Rapoport8abe7302010-12-18 17:43:19 -0500112#define CONFIG_SYS_NO_FLASH
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200113#define CONFIG_SYS_I2C
114#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
115#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
116#define CONFIG_SYS_I2C_OMAP34XX
Nikita Kiryanovb47cb9d2012-01-12 03:26:30 +0000117#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
118#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Nikita Kiryanova8eeecb2014-08-20 15:08:52 +0300119#define CONFIG_SYS_I2C_EEPROM_BUS 0
Nikita Kiryanovda4da302012-04-02 02:29:31 +0000120#define CONFIG_I2C_MULTI_BUS
Mike Rapoport8abe7302010-12-18 17:43:19 -0500121
122/*
123 * TWL4030
124 */
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000125#define CONFIG_TWL4030_POWER
126#define CONFIG_TWL4030_LED
Mike Rapoport8abe7302010-12-18 17:43:19 -0500127
128/*
129 * Board NAND Info.
130 */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500131#define CONFIG_NAND_OMAP_GPMC
132#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
133 /* to access nand */
134#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
135 /* to access nand at */
136 /* CS0 */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500137#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
138 /* devices */
Stefan Roese55503c12014-03-11 17:04:45 +0100139
Mike Rapoport8abe7302010-12-18 17:43:19 -0500140/* Environment information */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500141#define CONFIG_EXTRA_ENV_SETTINGS \
142 "loadaddr=0x82000000\0" \
143 "usbtty=cdc_acm\0" \
Nikita Kiryanove4361e92013-12-11 18:04:40 +0200144 "console=ttyO2,115200n8\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500145 "mpurate=500\0" \
146 "vram=12M\0" \
147 "dvimode=1024x768MR-16@60\0" \
148 "defaultdisplay=dvi\0" \
149 "mmcdev=0\0" \
150 "mmcroot=/dev/mmcblk0p2 rw\0" \
Igor Grinberg23964602013-04-22 01:06:55 +0000151 "mmcrootfstype=ext4 rootwait\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500152 "nandroot=/dev/mtdblock4 rw\0" \
Igor Grinberg23964602013-04-22 01:06:55 +0000153 "nandrootfstype=ubifs\0" \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500154 "mmcargs=setenv bootargs console=${console} " \
155 "mpurate=${mpurate} " \
156 "vram=${vram} " \
157 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500158 "omapdss.def_disp=${defaultdisplay} " \
159 "root=${mmcroot} " \
160 "rootfstype=${mmcrootfstype}\0" \
161 "nandargs=setenv bootargs console=${console} " \
162 "mpurate=${mpurate} " \
163 "vram=${vram} " \
164 "omapfb.mode=dvi:${dvimode} " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500165 "omapdss.def_disp=${defaultdisplay} " \
166 "root=${nandroot} " \
167 "rootfstype=${nandrootfstype}\0" \
168 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
169 "bootscript=echo Running bootscript from mmc ...; " \
170 "source ${loadaddr}\0" \
171 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
172 "mmcboot=echo Booting from mmc ...; " \
173 "run mmcargs; " \
174 "bootm ${loadaddr}\0" \
175 "nandboot=echo Booting from nand ...; " \
176 "run nandargs; " \
Igor Grinberg23964602013-04-22 01:06:55 +0000177 "nand read ${loadaddr} 2a0000 400000; " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500178 "bootm ${loadaddr}\0" \
179
180#define CONFIG_BOOTCOMMAND \
Andrew Bradforde1c7c8a2012-10-01 05:06:52 +0000181 "mmc dev ${mmcdev}; if mmc rescan; then " \
Mike Rapoport8abe7302010-12-18 17:43:19 -0500182 "if run loadbootscript; then " \
183 "run bootscript; " \
184 "else " \
185 "if run loaduimage; then " \
186 "run mmcboot; " \
187 "else run nandboot; " \
188 "fi; " \
189 "fi; " \
190 "else run nandboot; fi"
191
Mike Rapoport8abe7302010-12-18 17:43:19 -0500192/*
193 * Miscellaneous configurable options
194 */
Igor Grinbergc73b4f12011-04-18 17:48:28 -0400195#define CONFIG_AUTO_COMPLETE
196#define CONFIG_CMDLINE_EDITING
197#define CONFIG_TIMESTAMP
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000198#define CONFIG_SYS_AUTOLOAD "no"
Mike Rapoport8abe7302010-12-18 17:43:19 -0500199#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500200#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
201/* Print Buffer Size */
202#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203 sizeof(CONFIG_SYS_PROMPT) + 16)
204#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
205/* Boot Argument Buffer Size */
206#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
207
208#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
209 /* works on */
210#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
211 0x01F00000) /* 31MB */
212
213#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
214 /* load address */
215
216/*
217 * OMAP3 has 12 GP timers, they can be driven by the system clock
218 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
219 * This rate is divided by a local divisor.
220 */
221#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
222#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500223
224/*-----------------------------------------------------------------------
Mike Rapoport8abe7302010-12-18 17:43:19 -0500225 * Physical Memory Map
226 */
227#define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */
228#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Mike Rapoport8abe7302010-12-18 17:43:19 -0500229
Mike Rapoport8abe7302010-12-18 17:43:19 -0500230/*-----------------------------------------------------------------------
231 * FLASH and environment organization
232 */
233
234/* **** PISMO SUPPORT *** */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500235/* Monitor at start of flash */
236#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Igor Grinberg315ef7e2012-10-07 01:17:34 +0000237#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Mike Rapoport8abe7302010-12-18 17:43:19 -0500238
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000239#define CONFIG_ENV_IS_IN_NAND
Mike Rapoport8abe7302010-12-18 17:43:19 -0500240#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
Luca Ceresoli9783a2c2011-04-20 11:02:05 -0400241#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
Mike Rapoport8abe7302010-12-18 17:43:19 -0500242#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
243
Mike Rapoport8abe7302010-12-18 17:43:19 -0500244#if defined(CONFIG_CMD_NET)
Mike Rapoport8abe7302010-12-18 17:43:19 -0500245#define CONFIG_SMC911X
246#define CONFIG_SMC911X_32_BIT
Igor Grinberg05a96a42011-04-18 17:55:21 -0400247#define CM_T3X_SMC911X_BASE 0x2C000000
248#define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20))
249#define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE
Mike Rapoport8abe7302010-12-18 17:43:19 -0500250#endif /* (CONFIG_CMD_NET) */
251
252/* additions for new relocation code, must be added to all boards */
253#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
254#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
255#define CONFIG_SYS_INIT_RAM_SIZE 0x800
256#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
257 CONFIG_SYS_INIT_RAM_SIZE - \
258 GENERATED_GBL_DATA_SIZE)
259
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400260/* Status LED */
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000261#define CONFIG_STATUS_LED /* Status LED enabled */
262#define CONFIG_BOARD_SPECIFIC_LED
Igor Grinberg5ef7b862013-11-06 16:39:47 +0200263#define CONFIG_GPIO_LED
264#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
265#define GREEN_LED_DEV 0
266#define STATUS_LED_BIT GREEN_LED_GPIO
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400267#define STATUS_LED_STATE STATUS_LED_ON
268#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
Igor Grinberg5ef7b862013-11-06 16:39:47 +0200269#define STATUS_LED_BOOT GREEN_LED_DEV
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400270
Nikita Kiryanova6b2b732013-02-24 06:19:23 +0000271#define CONFIG_SPLASHIMAGE_GUARD
272
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400273/* GPIO banks */
274#ifdef CONFIG_STATUS_LED
Nikita Kiryanov0630b032012-01-02 04:01:30 +0000275#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
Igor Grinbergd2367bc2011-04-18 17:54:33 -0400276#endif
277
Nikita Kiryanov2247eb42013-01-30 21:39:58 +0000278/* Display Configuration */
279#define CONFIG_OMAP3_GPIO_2
Nikita Kiryanova6db6242013-12-31 12:55:15 +0200280#define CONFIG_OMAP3_GPIO_5
Nikita Kiryanov2247eb42013-01-30 21:39:58 +0000281#define CONFIG_VIDEO_OMAP3
282#define LCD_BPP LCD_COLOR16
283
284#define CONFIG_LCD
Nikita Kiryanovc4a295a2012-12-22 21:03:48 +0000285#define CONFIG_SPLASH_SCREEN
Nikita Kiryanov7f9ceea2015-01-14 10:42:54 +0200286#define CONFIG_SPLASH_SOURCE
Nikita Kiryanovc4a295a2012-12-22 21:03:48 +0000287#define CONFIG_CMD_BMP
288#define CONFIG_BMP_16BPP
Nikita Kiryanov25da1522013-10-16 17:23:29 +0300289#define CONFIG_SCF0403_LCD
290
291#define CONFIG_OMAP3_SPI
Nikita Kiryanov2247eb42013-01-30 21:39:58 +0000292
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100293/* Defines for SPL */
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100294#define CONFIG_SPL_FRAMEWORK
295#define CONFIG_SPL_NAND_SIMPLE
296
297#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
298#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
Paul Kocialkowski341e8cd2014-11-08 23:14:55 +0100299#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET602a16c2014-10-15 17:53:11 +0200300#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100301
302#define CONFIG_SPL_BOARD_INIT
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100303#define CONFIG_SPL_NAND_BASE
304#define CONFIG_SPL_NAND_DRIVERS
305#define CONFIG_SPL_NAND_ECC
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100306#define CONFIG_SPL_OMAP3_ID_NAND
307#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
308
309/* NAND boot config */
310#define CONFIG_SYS_NAND_5_ADDR_CYCLE
311#define CONFIG_SYS_NAND_PAGE_COUNT 64
312#define CONFIG_SYS_NAND_PAGE_SIZE 2048
313#define CONFIG_SYS_NAND_OOBSIZE 64
314#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
315#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
316/*
317 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
318 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
319 */
320#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
321 10, 11, 12 }
322#define CONFIG_SYS_NAND_ECCSIZE 512
323#define CONFIG_SYS_NAND_ECCBYTES 3
324#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
325
326#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
327#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
328
329#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinicfff4aa2016-08-26 13:30:43 -0400330#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
331 CONFIG_SPL_TEXT_BASE)
Stefan Roese8ef10bd2013-12-04 13:54:18 +0100332
333/*
334 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
335 * older x-loader implementations. And move the BSS area so that it
336 * doesn't overlap with TEXT_BASE.
337 */
338#define CONFIG_SYS_TEXT_BASE 0x80008000
339#define CONFIG_SPL_BSS_START_ADDR 0x80100000
340#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
341
342#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
343#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
344
Nikita Kiryanovd6554782016-04-16 17:55:09 +0300345/* EEPROM */
346#define CONFIG_CMD_EEPROM
347#define CONFIG_ENV_EEPROM_IS_ON_I2C
348#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
349#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
350#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
351#define CONFIG_SYS_EEPROM_SIZE 256
352
353#define CONFIG_CMD_EEPROM_LAYOUT
354#define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3"
355
Mike Rapoport8abe7302010-12-18 17:43:19 -0500356#endif /* __CONFIG_H */