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Timur Tabi9b45b5a2010-06-14 15:28:24 -05001/*
ramneek mehresh3d339632012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabi9b45b5a2010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabi9b45b5a2010-06-14 15:28:24 -05007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Matthew McClintockc4253e92012-05-18 06:04:17 +000014#ifdef CONFIG_SDCARD
Ying Zhangdfb2b152013-08-16 15:16:12 +080015#define CONFIG_SPL_MMC_MINIMAL
16#define CONFIG_SPL_FLUSH_IMAGE
17#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangdfb2b152013-08-16 15:16:12 +080018#define CONFIG_FSL_LAW /* Use common FSL init code */
19#define CONFIG_SYS_TEXT_BASE 0x11001000
20#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhang25daf572014-01-24 15:50:06 +080021#define CONFIG_SPL_PAD_TO 0x20000
22#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053023#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +080024#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
25#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080026#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +080027#define CONFIG_SYS_MPC85XX_NO_RESETVEC
28#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
29#define CONFIG_SPL_MMC_BOOT
30#ifdef CONFIG_SPL_BUILD
31#define CONFIG_SPL_COMMON_INIT_DDR
32#endif
Matthew McClintockc4253e92012-05-18 06:04:17 +000033#endif
34
35#ifdef CONFIG_SPIFLASH
Ying Zhang9b155ca2013-08-16 15:16:14 +080036#define CONFIG_SPL_SPI_FLASH_MINIMAL
37#define CONFIG_SPL_FLUSH_IMAGE
38#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang9b155ca2013-08-16 15:16:14 +080039#define CONFIG_FSL_LAW /* Use common FSL init code */
40#define CONFIG_SYS_TEXT_BASE 0x11001000
41#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhang25daf572014-01-24 15:50:06 +080042#define CONFIG_SPL_PAD_TO 0x20000
43#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053044#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang9b155ca2013-08-16 15:16:14 +080045#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
46#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhang25daf572014-01-24 15:50:06 +080047#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang9b155ca2013-08-16 15:16:14 +080048#define CONFIG_SYS_MPC85XX_NO_RESETVEC
49#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
50#define CONFIG_SPL_SPI_BOOT
51#ifdef CONFIG_SPL_BUILD
52#define CONFIG_SPL_COMMON_INIT_DDR
53#endif
Matthew McClintockc4253e92012-05-18 06:04:17 +000054#endif
55
Matthew McClintockcd99caa2013-02-18 10:02:19 +000056#define CONFIG_NAND_FSL_ELBC
York Sun4a343052013-12-17 11:21:08 -080057#define CONFIG_SYS_NAND_MAX_ECCPOS 56
58#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockcd99caa2013-02-18 10:02:19 +000059
60#ifdef CONFIG_NAND
Ying Zhang9c2e84f2013-08-16 15:16:16 +080061#ifdef CONFIG_TPL_BUILD
62#define CONFIG_SPL_NAND_BOOT
63#define CONFIG_SPL_FLUSH_IMAGE
Simon Glass7db65a82016-09-12 23:18:45 -060064#define CONFIG_SPL_NAND_INIT
Ying Zhang9c2e84f2013-08-16 15:16:16 +080065#define CONFIG_SPL_COMMON_INIT_DDR
66#define CONFIG_SPL_MAX_SIZE (128 << 10)
67#define CONFIG_SPL_TEXT_BASE 0xf8f81000
68#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053069#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang9c2e84f2013-08-16 15:16:16 +080070#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
71#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
72#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
73#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockcd99caa2013-02-18 10:02:19 +000074#define CONFIG_SPL_INIT_MINIMAL
Matthew McClintockcd99caa2013-02-18 10:02:19 +000075#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang9c2e84f2013-08-16 15:16:16 +080076#define CONFIG_SPL_TEXT_BASE 0xff800000
77#define CONFIG_SPL_MAX_SIZE 4096
78#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
79#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
80#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
81#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
82#endif
83#define CONFIG_SPL_PAD_TO 0x20000
84#define CONFIG_TPL_PAD_TO 0x20000
85#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
86#define CONFIG_SYS_TEXT_BASE 0x11001000
87#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockcd99caa2013-02-18 10:02:19 +000088#endif
89
Timur Tabi9b45b5a2010-06-14 15:28:24 -050090/* High Level Configuration Options */
91#define CONFIG_BOOKE /* BOOKE */
92#define CONFIG_E500 /* BOOKE e500 family */
Timur Tabi9b45b5a2010-06-14 15:28:24 -050093#define CONFIG_P1022
94#define CONFIG_P1022DS
95#define CONFIG_MP /* support multiple processors */
96
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020097#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahaf2036562014-01-14 11:34:26 +053098#define CONFIG_SYS_TEXT_BASE 0xeff40000
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020099#endif
100
Kumar Galae727a362011-01-12 02:48:53 -0600101#ifndef CONFIG_RESET_VECTOR_ADDRESS
102#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
103#endif
104
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500105#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
106#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Daya8099812016-05-03 19:52:49 -0400107#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
108#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
109#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500110#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
111#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
112#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
113
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500114#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabi6a873c92011-09-06 09:36:06 -0500115
116#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500117#define CONFIG_ADDR_MAP
118#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800119#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500120
121#define CONFIG_FSL_LAW /* Use common FSL init code */
122
123#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
124#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
125#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
126
127/*
128 * These can be toggled for performance analysis, otherwise use default.
129 */
130#define CONFIG_L2_CACHE
131#define CONFIG_BTB
132
133#define CONFIG_SYS_MEMTEST_START 0x00000000
134#define CONFIG_SYS_MEMTEST_END 0x7fffffff
135
Timur Tabid8f341c2011-08-04 18:03:41 -0500136#define CONFIG_SYS_CCSRBAR 0xffe00000
137#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500138
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000139/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
140 SPL code*/
141#ifdef CONFIG_SPL_BUILD
142#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
143#endif
144
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500145/* DDR Setup */
146#define CONFIG_DDR_SPD
147#define CONFIG_VERY_BIG_RAM
York Sunf0626592013-09-30 09:22:09 -0700148#define CONFIG_SYS_FSL_DDR3
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500149
150#ifdef CONFIG_DDR_ECC
151#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
152#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
153#endif
154
155#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
156#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
157
158#define CONFIG_NUM_DDR_CONTROLLERS 1
159#define CONFIG_DIMM_SLOTS_PER_CTLR 1
160#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
161
162/* I2C addresses of SPD EEPROMs */
163#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac68e86c2011-01-31 22:18:47 -0600164#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500165
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000166/* These are used when DDR doesn't use SPD. */
167#define CONFIG_SYS_SDRAM_SIZE 2048
168#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
169#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
170#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
171#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
172#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
173#define CONFIG_SYS_DDR_TIMING_3 0x00010000
174#define CONFIG_SYS_DDR_TIMING_0 0x40110104
175#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
176#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
177#define CONFIG_SYS_DDR_MODE_1 0x00441221
178#define CONFIG_SYS_DDR_MODE_2 0x00000000
179#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
180#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
181#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
182#define CONFIG_SYS_DDR_CONTROL 0xc7000008
183#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
184#define CONFIG_SYS_DDR_TIMING_4 0x00220001
185#define CONFIG_SYS_DDR_TIMING_5 0x02401400
186#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
187#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
188
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500189/*
190 * Memory map
191 *
192 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
193 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
194 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
195 *
196 * Localbus cacheable (TBD)
197 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
198 *
199 * Localbus non-cacheable
200 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
201 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000202 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500203 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
204 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
205 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
206 */
207
208/*
209 * Local Bus Definitions
210 */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000211#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800212#ifdef CONFIG_PHYS_64BIT
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000213#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800214#else
215#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
216#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500217
218#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000219 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500220#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
221
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000222#ifdef CONFIG_NAND
223#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
224#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
225#else
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500226#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
227#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000228#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500229
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000230#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500231#define CONFIG_SYS_FLASH_QUIET_TEST
232#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
233
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000234#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500235#define CONFIG_SYS_MAX_FLASH_SECT 1024
236
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000237#ifndef CONFIG_SYS_MONITOR_BASE
238#ifdef CONFIG_SPL_BUILD
239#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
240#else
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200241#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000242#endif
243#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500244
245#define CONFIG_FLASH_CFI_DRIVER
246#define CONFIG_SYS_FLASH_CFI
247#define CONFIG_SYS_FLASH_EMPTY_INFO
248
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000249/* Nand Flash */
250#if defined(CONFIG_NAND_FSL_ELBC)
251#define CONFIG_SYS_NAND_BASE 0xff800000
252#ifdef CONFIG_PHYS_64BIT
253#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
254#else
255#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
256#endif
257
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800258#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000259#define CONFIG_SYS_MAX_NAND_DEVICE 1
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000260#define CONFIG_CMD_NAND 1
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800261#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000262#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
263
264/* NAND flash config */
265#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
266 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
267 | BR_PS_8 /* Port Size = 8 bit */ \
268 | BR_MS_FCM /* MSEL = FCM */ \
269 | BR_V) /* valid */
270#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
271 | OR_FCM_PGS /* Large Page*/ \
272 | OR_FCM_CSCT \
273 | OR_FCM_CST \
274 | OR_FCM_CHT \
275 | OR_FCM_SCY_1 \
276 | OR_FCM_TRLX \
277 | OR_FCM_EHTR)
278#ifdef CONFIG_NAND
279#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
280#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
281#else
282#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
283#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
284#endif
285
286#endif /* CONFIG_NAND_FSL_ELBC */
287
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500288#define CONFIG_BOARD_EARLY_INIT_F
289#define CONFIG_BOARD_EARLY_INIT_R
290#define CONFIG_MISC_INIT_R
Timur Tabi8848d472010-07-21 16:56:19 -0500291#define CONFIG_HWCONFIG
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500292
293#define CONFIG_FSL_NGPIXIS
294#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutangb7738b52011-01-24 18:21:15 +0800295#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500296#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800297#else
298#define PIXIS_BASE_PHYS PIXIS_BASE
299#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500300
301#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
302#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
303
304#define PIXIS_LBMAP_SWITCH 7
York Sun362c9932011-01-26 10:30:00 -0800305#define PIXIS_LBMAP_MASK 0xF0
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500306#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000307#define PIXIS_SPD 0x07
308#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang382e3572011-02-24 16:11:56 +0800309#define PIXIS_ELBC_SPI_MASK 0xc0
310#define PIXIS_SPI 0x80
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500311
312#define CONFIG_SYS_INIT_RAM_LOCK
313#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200314#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500315
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500316#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200317 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500318#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
319
Prabhakar Kushwahaf4027312014-03-31 15:31:48 +0530320#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang5b5bd372011-11-02 09:16:44 +0800321#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500322
323/*
Ying Zhangdfb2b152013-08-16 15:16:12 +0800324 * Config the L2 Cache as L2 SRAM
325*/
326#if defined(CONFIG_SPL_BUILD)
Ying Zhang9b155ca2013-08-16 15:16:14 +0800327#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800328#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
329#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
330#define CONFIG_SYS_L2_SIZE (256 << 10)
331#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
332#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang3587a832014-01-24 15:50:08 +0800333#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800334#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang3587a832014-01-24 15:50:08 +0800335#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
336#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800337#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800338#elif defined(CONFIG_NAND)
339#ifdef CONFIG_TPL_BUILD
340#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
341#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
342#define CONFIG_SYS_L2_SIZE (256 << 10)
343#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
344#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
345#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
346#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
347#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
348#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
349#else
350#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
351#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
352#define CONFIG_SYS_L2_SIZE (256 << 10)
353#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
354#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
355#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
356#endif
Ying Zhangdfb2b152013-08-16 15:16:12 +0800357#endif
358#endif
359
360/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500361 * Serial Port
362 */
363#define CONFIG_CONS_INDEX 1
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500364#define CONFIG_SYS_NS16550_SERIAL
365#define CONFIG_SYS_NS16550_REG_SIZE 1
366#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangdfb2b152013-08-16 15:16:12 +0800367#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000368#define CONFIG_NS16550_MIN_FUNCTIONS
369#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500370
371#define CONFIG_SYS_BAUDRATE_TABLE \
372 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
373
374#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
375#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
376
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500377/* Video */
Timur Tabi32f709e2011-04-11 14:18:22 -0500378
Timur Tabi209c0722010-09-24 01:25:53 +0200379#ifdef CONFIG_FSL_DIU_FB
380#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
381#define CONFIG_VIDEO
382#define CONFIG_CMD_BMP
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500383#define CONFIG_CFB_CONSOLE
Timur Tabi020edd22011-02-15 17:09:19 -0600384#define CONFIG_VIDEO_SW_CURSOR
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500385#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabi209c0722010-09-24 01:25:53 +0200386#define CONFIG_VIDEO_LOGO
387#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi970c01f2010-09-16 16:35:44 -0500388#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
389/*
390 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
391 * disable empty flash sector detection, which is I/O-intensive.
392 */
393#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500394#endif
395
Timur Tabi32f709e2011-04-11 14:18:22 -0500396#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang6c698c02011-01-24 18:21:19 +0800397#endif
398
399#ifdef CONFIG_ATI
400#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
401#define CONFIG_VIDEO
402#define CONFIG_BIOSEMU
403#define CONFIG_VIDEO_SW_CURSOR
404#define CONFIG_ATI_RADEON_FB
405#define CONFIG_VIDEO_LOGO
406#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
407#define CONFIG_CFB_CONSOLE
408#define CONFIG_VGA_AS_SINGLE_DEVICE
409#endif
410
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500411/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200412#define CONFIG_SYS_I2C
413#define CONFIG_SYS_I2C_FSL
414#define CONFIG_SYS_FSL_I2C_SPEED 400000
415#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
416#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
417#define CONFIG_SYS_FSL_I2C2_SPEED 400000
418#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
419#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500420#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500421
422/*
423 * I2C2 EEPROM
424 */
425#define CONFIG_ID_EEPROM
426#define CONFIG_SYS_I2C_EEPROM_NXID
427#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
428#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
429#define CONFIG_SYS_EEPROM_BUS_NUM 1
430
431/*
Jiang Yutang382e3572011-02-24 16:11:56 +0800432 * eSPI - Enhanced SPI
433 */
Jiang Yutang382e3572011-02-24 16:11:56 +0800434
435#define CONFIG_HARD_SPI
Jiang Yutang382e3572011-02-24 16:11:56 +0800436
Jiang Yutang382e3572011-02-24 16:11:56 +0800437#define CONFIG_SF_DEFAULT_SPEED 10000000
438#define CONFIG_SF_DEFAULT_MODE 0
439
440/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500441 * General PCI
442 * Memory space is mapped 1-1, but I/O space must start from 0.
443 */
444
445/* controller 1, Slot 2, tgtid 1, Base address a000 */
446#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800447#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500448#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
449#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800450#else
451#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
452#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
453#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500454#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
455#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
456#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800457#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500458#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800459#else
460#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
461#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500462#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
463
464/* controller 2, direct to uli, tgtid 2, Base address 9000 */
465#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800466#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500467#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
468#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800469#else
470#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
471#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
472#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500473#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
474#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
475#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800476#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500477#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800478#else
479#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
480#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500481#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
482
483/* controller 3, Slot 1, tgtid 3, Base address b000 */
484#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800485#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500486#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
487#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800488#else
489#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
490#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
491#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500492#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
493#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
494#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutangb7738b52011-01-24 18:21:15 +0800495#ifdef CONFIG_PHYS_64BIT
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500496#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutangb7738b52011-01-24 18:21:15 +0800497#else
498#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
499#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500500#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
501
502#ifdef CONFIG_PCI
Gabor Juhosb4458732013-05-30 07:06:12 +0000503#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500504#define CONFIG_PCI_PNP /* do pci plug-and-play */
505#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
506#endif
507
508/* SATA */
509#define CONFIG_LIBATA
510#define CONFIG_FSL_SATA
Zang Roy-R619112ce421a2012-11-26 00:05:38 +0000511#define CONFIG_FSL_SATA_V2
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500512
513#define CONFIG_SYS_SATA_MAX_DEVICE 2
514#define CONFIG_SATA1
515#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
516#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
517#define CONFIG_SATA2
518#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
519#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
520
521#ifdef CONFIG_FSL_SATA
522#define CONFIG_LBA48
523#define CONFIG_CMD_SATA
524#define CONFIG_DOS_PARTITION
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500525#endif
526
527#define CONFIG_MMC
528#ifdef CONFIG_MMC
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500529#define CONFIG_FSL_ESDHC
530#define CONFIG_GENERIC_MMC
531#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
532#endif
533
534#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500535#define CONFIG_DOS_PARTITION
536#endif
537
538#define CONFIG_TSEC_ENET
539#ifdef CONFIG_TSEC_ENET
540
541#define CONFIG_TSECV2
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500542
543#define CONFIG_MII /* MII PHY management */
544#define CONFIG_TSEC1 1
545#define CONFIG_TSEC1_NAME "eTSEC1"
546#define CONFIG_TSEC2 1
547#define CONFIG_TSEC2_NAME "eTSEC2"
548
549#define TSEC1_PHY_ADDR 1
550#define TSEC2_PHY_ADDR 2
551
552#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
553#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
554
555#define TSEC1_PHYIDX 0
556#define TSEC2_PHYIDX 0
557
558#define CONFIG_ETHPRIME "eTSEC1"
559
560#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
561#endif
562
563/*
Yangbo Lu140b2bb2014-10-16 10:58:55 +0800564 * Dynamic MTD Partition support with mtdparts
565 */
566#define CONFIG_MTD_DEVICE
567#define CONFIG_MTD_PARTITIONS
568#define CONFIG_CMD_MTDPARTS
569#define CONFIG_FLASH_CFI_MTD
570#ifdef CONFIG_PHYS_64BIT
571#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
572#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
573 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
574 "512k(dtb),768k(u-boot)"
575#else
576#define MTDIDS_DEFAULT "nor0=e8000000.nor"
577#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
578 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
579 "512k(dtb),768k(u-boot)"
580#endif
581
582/*
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500583 * Environment
584 */
Ying Zhang9b155ca2013-08-16 15:16:14 +0800585#ifdef CONFIG_SPIFLASH
Matthew McClintockc4253e92012-05-18 06:04:17 +0000586#define CONFIG_ENV_IS_IN_SPI_FLASH
587#define CONFIG_ENV_SPI_BUS 0
588#define CONFIG_ENV_SPI_CS 0
589#define CONFIG_ENV_SPI_MAX_HZ 10000000
590#define CONFIG_ENV_SPI_MODE 0
591#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
592#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
593#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhangdfb2b152013-08-16 15:16:12 +0800594#elif defined(CONFIG_SDCARD)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000595#define CONFIG_ENV_IS_IN_MMC
Ying Zhangdfb2b152013-08-16 15:16:12 +0800596#define CONFIG_FSL_FIXED_MMC_LOCATION
Matthew McClintockc4253e92012-05-18 06:04:17 +0000597#define CONFIG_ENV_SIZE 0x2000
598#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000599#elif defined(CONFIG_NAND)
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800600#ifdef CONFIG_TPL_BUILD
601#define CONFIG_ENV_SIZE 0x2000
602#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
603#else
Matthew McClintockc4253e92012-05-18 06:04:17 +0000604#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang9c2e84f2013-08-16 15:16:16 +0800605#endif
606#define CONFIG_ENV_IS_IN_NAND
607#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000608#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockcd99caa2013-02-18 10:02:19 +0000609#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockc4253e92012-05-18 06:04:17 +0000610#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
611#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
612#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockc4253e92012-05-18 06:04:17 +0000613#else
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500614#define CONFIG_ENV_IS_IN_FLASH
Matthew McClintockc4253e92012-05-18 06:04:17 +0000615#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500616#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockc4253e92012-05-18 06:04:17 +0000617#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
618#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500619
620#define CONFIG_LOADS_ECHO
621#define CONFIG_SYS_LOADS_BAUD_CHANGE
622
623/*
624 * Command line configuration.
625 */
Kumar Gala5900ea72010-06-09 22:59:41 -0500626#define CONFIG_CMD_ERRATA
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500627#define CONFIG_CMD_IRQ
Matthew McClintock49b9da12010-12-17 17:26:41 -0600628#define CONFIG_CMD_REGINFO
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500629
630#ifdef CONFIG_PCI
631#define CONFIG_CMD_PCI
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500632#endif
633
634/*
635 * USB
636 */
ramneek mehresh3d339632012-04-18 19:39:53 +0000637#define CONFIG_HAS_FSL_DR_USB
638#ifdef CONFIG_HAS_FSL_DR_USB
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500639#define CONFIG_USB_EHCI
640
641#ifdef CONFIG_USB_EHCI
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500642#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
643#define CONFIG_USB_EHCI_FSL
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500644#endif
ramneek mehresh3d339632012-04-18 19:39:53 +0000645#endif
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500646
647/*
648 * Miscellaneous configurable options
649 */
650#define CONFIG_SYS_LONGHELP /* undef to save memory */
651#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500652#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500653#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500654#ifdef CONFIG_CMD_KGDB
655#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
656#else
657#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
658#endif
659/* Print Buffer Size */
660#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
661#define CONFIG_SYS_MAXARGS 16
662#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500663
664/*
665 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500666 * have to be in the first 64 MB of memory, since this is
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500667 * the maximum mapped by the Linux kernel during initialization.
668 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500669#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
670#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500671
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500672#ifdef CONFIG_CMD_KGDB
673#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500674#endif
675
676/*
677 * Environment Configuration
678 */
679
680#define CONFIG_HOSTNAME p1022ds
Joe Hershberger257ff782011-10-13 13:03:47 +0000681#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000682#define CONFIG_BOOTFILE "uImage"
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500683#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
684
685#define CONFIG_LOADADDR 1000000
686
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500687
688#define CONFIG_BAUDRATE 115200
689
Timur Tabi1a70b232012-05-04 12:21:29 +0000690#define CONFIG_EXTRA_ENV_SETTINGS \
691 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200692 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
693 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi1a70b232012-05-04 12:21:29 +0000694 "tftpflash=tftpboot $loadaddr $uboot && " \
695 "protect off $ubootaddr +$filesize && " \
696 "erase $ubootaddr +$filesize && " \
697 "cp.b $loadaddr $ubootaddr $filesize && " \
698 "protect on $ubootaddr +$filesize && " \
699 "cmp.b $loadaddr $ubootaddr $filesize\0" \
700 "consoledev=ttyS0\0" \
701 "ramdiskaddr=2000000\0" \
702 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500703 "fdtaddr=1e00000\0" \
Timur Tabi1a70b232012-05-04 12:21:29 +0000704 "fdtfile=p1022ds.dtb\0" \
705 "bdev=sda3\0" \
Timur Tabi32f709e2011-04-11 14:18:22 -0500706 "hwconfig=esdhc;audclk:12\0"
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500707
708#define CONFIG_HDBOOT \
709 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000710 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500711 "tftp $loadaddr $bootfile;" \
712 "tftp $fdtaddr $fdtfile;" \
713 "bootm $loadaddr - $fdtaddr"
714
715#define CONFIG_NFSBOOTCOMMAND \
716 "setenv bootargs root=/dev/nfs rw " \
717 "nfsroot=$serverip:$rootpath " \
718 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000719 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500720 "tftp $loadaddr $bootfile;" \
721 "tftp $fdtaddr $fdtfile;" \
722 "bootm $loadaddr - $fdtaddr"
723
724#define CONFIG_RAMBOOTCOMMAND \
725 "setenv bootargs root=/dev/ram rw " \
Timur Tabi1a70b232012-05-04 12:21:29 +0000726 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabi9b45b5a2010-06-14 15:28:24 -0500727 "tftp $ramdiskaddr $ramdiskfile;" \
728 "tftp $loadaddr $bootfile;" \
729 "tftp $fdtaddr $fdtfile;" \
730 "bootm $loadaddr $ramdiskaddr $fdtaddr"
731
732#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
733
734#endif