Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 1 | /* |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 2 | * Copyright 2008-2012 Freescale Semiconductor, Inc. |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | bd8ec7e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <command.h> |
| 9 | #include <pci.h> |
| 10 | #include <asm/processor.h> |
| 11 | #include <asm/mmu.h> |
Kumar Gala | f81f89f | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 12 | #include <asm/cache.h> |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 13 | #include <asm/immap_85xx.h> |
Kumar Gala | 9bbd643 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 14 | #include <asm/fsl_pci.h> |
York Sun | f062659 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 15 | #include <fsl_ddr_sdram.h> |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 16 | #include <asm/io.h> |
Kumar Gala | 0edddd9 | 2010-04-20 10:21:12 -0500 | [diff] [blame] | 17 | #include <asm/fsl_serdes.h> |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 18 | #include <spd.h> |
| 19 | #include <miiphy.h> |
| 20 | #include <libfdt.h> |
| 21 | #include <spd_sdram.h> |
| 22 | #include <fdt_support.h> |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 23 | #include <fsl_mdio.h> |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 24 | #include <tsec.h> |
| 25 | #include <netdev.h> |
Wolfgang Denk | 5106862 | 2009-01-28 09:25:31 +0100 | [diff] [blame] | 26 | #include <sata.h> |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 27 | |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 28 | #include "../common/sgmii_riser.h" |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 29 | |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 30 | int board_early_init_f (void) |
| 31 | { |
| 32 | #ifdef CONFIG_MMC |
| 33 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 34 | |
| 35 | setbits_be32(&gur->pmuxcr, |
Xie Xiaobo | 8f3933e | 2011-10-03 12:18:39 -0700 | [diff] [blame] | 36 | (MPC85xx_PMUXCR_SDHC_CD | |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 37 | MPC85xx_PMUXCR_SDHC_WP)); |
Xie Xiaobo | 0912b33 | 2011-10-03 12:18:40 -0700 | [diff] [blame] | 38 | |
| 39 | /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, |
| 40 | * however, this erratum only applies to MPC8536 Rev1.0. |
| 41 | * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ |
| 42 | if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && |
| 43 | (SVR_MIN(get_svr()) >= 0x1)) |
| 44 | || (SVR_MAJ(get_svr() & 0x7) > 0x1)) |
| 45 | setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); |
Andy Fleming | 6843a6e | 2008-10-30 16:51:33 -0500 | [diff] [blame] | 46 | #endif |
| 47 | return 0; |
| 48 | } |
| 49 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 50 | int checkboard (void) |
| 51 | { |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 52 | u8 vboot; |
| 53 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 54 | |
Timur Tabi | 56953ee | 2012-03-15 11:42:27 +0000 | [diff] [blame] | 55 | printf("Board: MPC8536DS Sys ID: 0x%02x, " |
Kumar Gala | e21db03 | 2009-07-14 22:42:01 -0500 | [diff] [blame] | 56 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
| 57 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
| 58 | in_8(pixis_base + PIXIS_PVER)); |
| 59 | |
| 60 | vboot = in_8(pixis_base + PIXIS_VBOOT); |
| 61 | switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { |
| 62 | case PIXIS_VBOOT_LBMAP_NOR0: |
| 63 | puts ("vBank: 0\n"); |
| 64 | break; |
| 65 | case PIXIS_VBOOT_LBMAP_NOR1: |
| 66 | puts ("vBank: 1\n"); |
| 67 | break; |
| 68 | case PIXIS_VBOOT_LBMAP_NOR2: |
| 69 | puts ("vBank: 2\n"); |
| 70 | break; |
| 71 | case PIXIS_VBOOT_LBMAP_NOR3: |
| 72 | puts ("vBank: 3\n"); |
| 73 | break; |
| 74 | case PIXIS_VBOOT_LBMAP_PJET: |
| 75 | puts ("Promjet\n"); |
| 76 | break; |
| 77 | case PIXIS_VBOOT_LBMAP_NAND: |
| 78 | puts ("NAND\n"); |
| 79 | break; |
| 80 | } |
| 81 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 82 | return 0; |
| 83 | } |
| 84 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 85 | #if !defined(CONFIG_SPD_EEPROM) |
| 86 | /* |
| 87 | * Fixed sdram init -- doesn't use serial presence detect. |
| 88 | */ |
| 89 | |
| 90 | phys_size_t fixed_sdram (void) |
| 91 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
York Sun | a21803d | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 93 | struct ccsr_ddr __iomem *ddr = &immap->im_ddr; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 94 | uint d_init; |
| 95 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; |
| 97 | ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 98 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
| 100 | ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
| 101 | ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
| 102 | ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
| 103 | ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; |
| 104 | ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; |
| 105 | ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
| 106 | ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; |
| 107 | ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; |
| 108 | ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 109 | |
| 110 | #if defined (CONFIG_DDR_ECC) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 111 | ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; |
| 112 | ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; |
| 113 | ddr->err_sbe = CONFIG_SYS_DDR_SBE; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 114 | #endif |
| 115 | asm("sync;isync"); |
| 116 | |
| 117 | udelay(500); |
| 118 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 120 | |
| 121 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 122 | d_init = 1; |
| 123 | debug("DDR - 1st controller: memory initializing\n"); |
| 124 | /* |
| 125 | * Poll until memory is initialized. |
| 126 | * 512 Meg at 400 might hit this 200 times or so. |
| 127 | */ |
| 128 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { |
| 129 | udelay(1000); |
| 130 | } |
| 131 | debug("DDR: memory initialized\n\n"); |
| 132 | asm("sync; isync"); |
| 133 | udelay(500); |
| 134 | #endif |
| 135 | |
| 136 | return 512 * 1024 * 1024; |
| 137 | } |
| 138 | |
| 139 | #endif |
| 140 | |
| 141 | #ifdef CONFIG_PCI1 |
| 142 | static struct pci_controller pci1_hose; |
| 143 | #endif |
| 144 | |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 145 | #ifdef CONFIG_PCI |
| 146 | void pci_init_board(void) |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 147 | { |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 148 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 149 | struct fsl_pci_info pci_info; |
| 150 | u32 devdisr, pordevsr; |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 151 | u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 152 | int first_free_busno; |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 153 | |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 154 | first_free_busno = fsl_pcie_init_board(0); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 155 | |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 156 | #ifdef CONFIG_PCI1 |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 157 | devdisr = in_be32(&gur->devdisr); |
| 158 | pordevsr = in_be32(&gur->pordevsr); |
| 159 | porpllsr = in_be32(&gur->porpllsr); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 160 | |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 161 | pci_speed = 66666000; |
| 162 | pci_32 = 1; |
| 163 | pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; |
| 164 | pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 165 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 166 | if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 167 | SET_STD_PCI_INFO(pci_info, 1); |
| 168 | set_next_law(pci_info.mem_phys, |
| 169 | law_size_bits(pci_info.mem_size), pci_info.law); |
| 170 | set_next_law(pci_info.io_phys, |
| 171 | law_size_bits(pci_info.io_size), pci_info.law); |
| 172 | |
| 173 | pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); |
Peter Tyser | 2b91f71 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 174 | printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 175 | (pci_32) ? 32 : 64, |
| 176 | (pci_speed == 33333000) ? "33" : |
| 177 | (pci_speed == 66666000) ? "66" : "unknown", |
| 178 | pci_clk_sel ? "sync" : "async", |
| 179 | pci_agent ? "agent" : "host", |
| 180 | pci_arb ? "arbiter" : "external-arbiter", |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 181 | pci_info.regs); |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 182 | |
Kumar Gala | 06bea37 | 2010-12-17 15:14:54 -0600 | [diff] [blame] | 183 | first_free_busno = fsl_pci_init_port(&pci_info, |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 184 | &pci1_hose, first_free_busno); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 185 | } else { |
Peter Tyser | 2b91f71 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 186 | printf("PCI: disabled\n"); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 187 | } |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 188 | |
| 189 | puts("\n"); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 190 | #else |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 191 | setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 192 | #endif |
| 193 | } |
Mingkai Hu | a83eab2 | 2009-10-28 10:49:31 +0800 | [diff] [blame] | 194 | #endif |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 195 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 196 | int board_early_init_r(void) |
| 197 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
Kumar Gala | 040e418 | 2009-11-13 09:25:07 -0600 | [diff] [blame] | 199 | const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 200 | |
| 201 | /* |
| 202 | * Remap Boot flash + PROMJET region to caching-inhibited |
| 203 | * so that flash can be erased properly. |
| 204 | */ |
| 205 | |
Kumar Gala | f81f89f | 2008-09-22 14:11:11 -0500 | [diff] [blame] | 206 | /* Flush d-cache and invalidate i-cache of any FLASH data */ |
Wolfgang Denk | 82f15f3 | 2008-11-02 16:14:22 +0100 | [diff] [blame] | 207 | flush_dcache(); |
| 208 | invalidate_icache(); |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 209 | |
| 210 | /* invalidate existing TLB entry for flash + promjet */ |
| 211 | disable_tlb(flash_esel); |
| 212 | |
Kumar Gala | 4be8b57 | 2008-12-02 14:19:34 -0600 | [diff] [blame] | 213 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 214 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ |
| 215 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ |
| 216 | |
| 217 | return 0; |
| 218 | } |
| 219 | |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 220 | int board_eth_init(bd_t *bis) |
| 221 | { |
| 222 | #ifdef CONFIG_TSEC_ENET |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 223 | struct fsl_pq_mdio_info mdio_info; |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 224 | struct tsec_info_struct tsec_info[2]; |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 225 | int num = 0; |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 226 | |
| 227 | #ifdef CONFIG_TSEC1 |
| 228 | SET_STD_TSEC_INFO(tsec_info[num], 1); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 229 | if (is_serdes_configured(SGMII_TSEC1)) { |
| 230 | puts("eTSEC1 is in sgmii mode.\n"); |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 231 | tsec_info[num].phyaddr = 0; |
| 232 | tsec_info[num].flags |= TSEC_SGMII; |
| 233 | } |
| 234 | num++; |
| 235 | #endif |
| 236 | #ifdef CONFIG_TSEC3 |
| 237 | SET_STD_TSEC_INFO(tsec_info[num], 3); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 238 | if (is_serdes_configured(SGMII_TSEC3)) { |
| 239 | puts("eTSEC3 is in sgmii mode.\n"); |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 240 | tsec_info[num].phyaddr = 1; |
| 241 | tsec_info[num].flags |= TSEC_SGMII; |
| 242 | } |
| 243 | num++; |
| 244 | #endif |
| 245 | |
| 246 | if (!num) { |
| 247 | printf("No TSECs initialized\n"); |
| 248 | return 0; |
| 249 | } |
| 250 | |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 251 | #ifdef CONFIG_FSL_SGMII_RISER |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 252 | if (is_serdes_configured(SGMII_TSEC1) || |
| 253 | is_serdes_configured(SGMII_TSEC3)) { |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 254 | fsl_sgmii_riser_init(tsec_info, num); |
Kumar Gala | e6dc484 | 2010-12-16 14:28:06 -0600 | [diff] [blame] | 255 | } |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 256 | #endif |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 257 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 258 | mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; |
| 259 | mdio_info.name = DEFAULT_MII_NAME; |
| 260 | fsl_pq_mdio_init(bis, &mdio_info); |
| 261 | |
Jason Jin | 21181fd | 2008-10-10 11:41:00 +0800 | [diff] [blame] | 262 | tsec_eth_init(bis, tsec_info, num); |
| 263 | #endif |
| 264 | return pci_eth_init(bis); |
| 265 | } |
| 266 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 267 | #if defined(CONFIG_OF_BOARD_SETUP) |
Kumar Gala | c10a0c4 | 2008-10-21 08:28:33 -0500 | [diff] [blame] | 268 | void ft_board_setup(void *blob, bd_t *bd) |
| 269 | { |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 270 | ft_cpu_setup(blob, bd); |
| 271 | |
Kumar Gala | d0f27d3 | 2010-07-08 22:37:44 -0500 | [diff] [blame] | 272 | FT_FSL_PCI_SETUP; |
| 273 | |
Andy Fleming | acaccae | 2008-12-05 20:10:22 -0600 | [diff] [blame] | 274 | #ifdef CONFIG_FSL_SGMII_RISER |
| 275 | fsl_sgmii_riser_fdt_fixup(blob); |
| 276 | #endif |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 277 | |
| 278 | #ifdef CONFIG_HAS_FSL_MPH_USB |
| 279 | fdt_fixup_dr_usb(blob, bd); |
| 280 | #endif |
| 281 | |
Kumar Gala | fd83aa8 | 2008-07-25 13:31:05 -0500 | [diff] [blame] | 282 | } |
| 283 | #endif |