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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Linus Walleij717b0a82012-08-04 05:21:28 +00002/*
3 * (C) Copyright 2012
4 * Linaro
5 * Linus Walleij <linus.walleij@linaro.org>
6 * Common ARM Integrator configuration settings
Linus Walleij717b0a82012-08-04 05:21:28 +00007 */
8
Linus Walleij717b0a82012-08-04 05:21:28 +00009#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */
Linus Walleij717b0a82012-08-04 05:21:28 +000010
Linus Walleij717b0a82012-08-04 05:21:28 +000011/*
Linus Walleij717b0a82012-08-04 05:21:28 +000012 * The ARM boot monitor initializes the board.
13 * However, the default U-Boot code also performs the initialization.
14 * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
15 * - see documentation supplied with board for details of how to choose the
16 * image to run at reset/power up
17 * e.g. whether the ARM Boot Monitor runs before U-Boot
18 */
Linus Walleij717b0a82012-08-04 05:21:28 +000019
20/*
21 * The ARM boot monitor does not relocate U-Boot.
22 * However, the default U-Boot code performs the relocation check,
23 * and may relocate the code if the memory map is changed.
24 * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
25 */
26/* #define SKIP_CONFIG_RELOCATE_UBOOT */
27
Linus Walleij717b0a82012-08-04 05:21:28 +000028/*
29 * Physical Memory Map
30 */
Linus Walleij717b0a82012-08-04 05:21:28 +000031#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
32#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
33#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
34#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
35#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
36 CONFIG_SYS_INIT_RAM_SIZE - \
37 GENERATED_GBL_DATA_SIZE)
38#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
Linus Walleij48fd6152015-04-05 01:48:33 +020039
40/*
41 * FLASH and environment organization
42 * Top varies according to amount fitted
43 * Reserve top 4 blocks of flash
44 * - ARM Boot Monitor
45 * - Unused
46 * - SIB block
47 * - U-Boot environment
48 */
Linus Walleij48fd6152015-04-05 01:48:33 +020049#define CONFIG_SYS_FLASH_BASE 0x24000000
Linus Walleij48fd6152015-04-05 01:48:33 +020050
51/* Timeout values in ticks */
52#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
53#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
Linus Walleij48fd6152015-04-05 01:48:33 +020054#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */