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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dirk Behmebb732be2009-01-28 21:39:58 +01002/*
Tom Rini988a2352011-11-18 12:48:09 +00003 * (C) Copyright 2004-2011
Dirk Behmebb732be2009-01-28 21:39:58 +01004 * Texas Instruments, <www.ti.com>
5 *
6 * Author :
7 * Manikandan Pillai <mani.pillai@ti.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
Dirk Behmebb732be2009-01-28 21:39:58 +010012 */
Tom Rinid7247db2024-04-30 20:43:02 -060013#include <config.h>
Derald D. Woods1b01bf92017-08-06 00:00:21 -050014#include <dm.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060015#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -060016#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -060017#include <net.h>
Derald D. Woods1b01bf92017-08-06 00:00:21 -050018#include <ns16550.h>
Simon Glass36736182019-11-14 12:57:24 -070019#include <serial.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060020#include <asm/global_data.h>
Dirk Behmebb732be2009-01-28 21:39:58 +010021#include <asm/io.h>
22#include <asm/arch/mem.h>
23#include <asm/arch/mux.h>
24#include <asm/arch/sys_proto.h>
Vaibhav Hiremath4fdf2b72011-09-03 21:42:35 -040025#include <asm/arch/mmc_host_def.h>
Sanjeev Premi7b3dc822011-09-08 10:51:01 -040026#include <asm/gpio.h>
Paul Kocialkowski69559892014-11-08 20:55:47 +010027#include <twl4030.h>
Dirk Behmebb732be2009-01-28 21:39:58 +010028#include <asm/mach-types.h>
Simon Glassdbd79542020-05-10 11:40:11 -060029#include <linux/delay.h>
Masahiro Yamada2b7a8732017-11-30 13:45:24 +090030#include <linux/mtd/rawnand.h>
Dirk Behmebb732be2009-01-28 21:39:58 +010031#include "evm.h"
32
Derald D. Woods1b01bf92017-08-06 00:00:21 -050033#define OMAP3EVM_GPIO_ETH_RST_GEN1 64
34#define OMAP3EVM_GPIO_ETH_RST_GEN2 7
Sriramakrishnan0f188c32011-07-18 09:21:55 -040035
Tom Rini364d0022023-01-10 11:19:45 -050036#define CFG_SMC911X_BASE 0x2C000000
Derald D. Woods9aa45bc2020-07-18 19:23:04 -050037
John Rigby0d21ed02010-12-20 18:27:51 -070038DECLARE_GLOBAL_DATA_PTR;
39
Dirk Behme85ed7092010-12-18 07:40:28 +010040static u32 omap3_evm_version;
Ajay Kumar Gupta13fc2bd2010-06-10 11:20:49 +053041
Dirk Behme85ed7092010-12-18 07:40:28 +010042u32 get_omap3_evm_rev(void)
Ajay Kumar Gupta13fc2bd2010-06-10 11:20:49 +053043{
44 return omap3_evm_version;
45}
46
47static void omap3_evm_get_revision(void)
48{
Derald D. Woods9aa45bc2020-07-18 19:23:04 -050049#if defined(CONFIG_SMC911X)
Sanjeev Premi88105fb2010-11-04 16:02:32 -040050 /*
51 * Board revision can be ascertained only by identifying
52 * the Ethernet chipset.
53 */
Ajay Kumar Gupta13fc2bd2010-06-10 11:20:49 +053054 unsigned int smsc_id;
55
56 /* Ethernet PHY ID is stored at ID_REV register */
Tom Rini364d0022023-01-10 11:19:45 -050057 smsc_id = readl(CFG_SMC911X_BASE + 0x50) & 0xFFFF0000;
Ajay Kumar Gupta13fc2bd2010-06-10 11:20:49 +053058 printf("Read back SMSC id 0x%x\n", smsc_id);
59
60 switch (smsc_id) {
61 /* SMSC9115 chipset */
62 case 0x01150000:
63 omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
64 break;
65 /* SMSC 9220 chipset */
66 case 0x92200000:
67 default:
68 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
69 }
Derald D. Woods9aa45bc2020-07-18 19:23:04 -050070#else /* !CONFIG_SMC911X */
Sanjeev Premi88105fb2010-11-04 16:02:32 -040071#if defined(CONFIG_STATIC_BOARD_REV)
Derald D. Woods1b01bf92017-08-06 00:00:21 -050072 /* Look for static defintion of the board revision */
Sanjeev Premi88105fb2010-11-04 16:02:32 -040073 omap3_evm_version = CONFIG_STATIC_BOARD_REV;
74#else
Derald D. Woods1b01bf92017-08-06 00:00:21 -050075 /* Fallback to the default above */
Sanjeev Premi88105fb2010-11-04 16:02:32 -040076 omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
Derald D. Woods1b01bf92017-08-06 00:00:21 -050077#endif /* CONFIG_STATIC_BOARD_REV */
Derald D. Woods9aa45bc2020-07-18 19:23:04 -050078#endif /* CONFIG_SMC911X */
Ajay Kumar Gupta13fc2bd2010-06-10 11:20:49 +053079}
80
Derald D. Woods1b01bf92017-08-06 00:00:21 -050081#if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
82/* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
Ajay Kumar Guptaaeeac6b2010-06-10 11:20:50 +053083u8 omap3_evm_need_extvbus(void)
84{
85 u8 retval = 0;
86
87 if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
88 retval = 1;
89
90 return retval;
91}
Derald D. Woods1b01bf92017-08-06 00:00:21 -050092#endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
Ajay Kumar Guptaaeeac6b2010-06-10 11:20:50 +053093
94/*
Dirk Behmebb732be2009-01-28 21:39:58 +010095 * Routine: board_init
96 * Description: Early hardware init.
Tom Rix558bb832009-04-01 22:02:20 -050097 */
Dirk Behmebb732be2009-01-28 21:39:58 +010098int board_init(void)
99{
Dirk Behmebb732be2009-01-28 21:39:58 +0100100 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
101 /* board id for Linux */
102 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
103 /* boot param addr */
104 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
105
106 return 0;
107}
108
Derald D. Woods17f8f982017-09-02 17:43:05 -0500109#if defined(CONFIG_SPL_OS_BOOT)
110int spl_start_uboot(void)
111{
112 /* break into full u-boot on 'c' */
113 if (serial_tstc() && serial_getc() == 'c')
114 return 1;
115
116 return 0;
117}
118#endif /* CONFIG_SPL_OS_BOOT */
119
Derald D. Woods1b01bf92017-08-06 00:00:21 -0500120#if defined(CONFIG_SPL_BUILD)
Tom Rini988a2352011-11-18 12:48:09 +0000121/*
122 * Routine: get_board_mem_timings
123 * Description: If we use SPL then there is no x-loader nor config header
124 * so we have to setup the DDR timings ourself on the first bank. This
125 * provides the timing values back to the function that configures
126 * the memory.
127 */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000128void get_board_mem_timings(struct board_sdrc_timings *timings)
Tom Rini988a2352011-11-18 12:48:09 +0000129{
130 int pop_mfr, pop_id;
131
132 /*
133 * We need to identify what PoP memory is on the board so that
134 * we know what timings to use. To map the ID values please see
135 * nand_ids.c
136 */
137 identify_nand_chip(&pop_mfr, &pop_id);
138
139 if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
140 /* 256MB DDR */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000141 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
142 timings->ctrla = HYNIX_V_ACTIMA_200;
143 timings->ctrlb = HYNIX_V_ACTIMB_200;
Tom Rini988a2352011-11-18 12:48:09 +0000144 } else {
145 /* 128MB DDR */
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000146 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
147 timings->ctrla = MICRON_V_ACTIMA_165;
148 timings->ctrlb = MICRON_V_ACTIMB_165;
Tom Rini988a2352011-11-18 12:48:09 +0000149 }
Peter Baradaedb5c2f2012-11-13 07:40:28 +0000150 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
151 timings->mr = MICRON_V_MR_165;
Tom Rini988a2352011-11-18 12:48:09 +0000152}
Derald D. Woods1b01bf92017-08-06 00:00:21 -0500153#endif /* CONFIG_SPL_BUILD */
154
Tom Rix558bb832009-04-01 22:02:20 -0500155/*
Dirk Behmebb732be2009-01-28 21:39:58 +0100156 * Routine: misc_init_r
157 * Description: Init ethernet (done here so udelay works)
Tom Rix558bb832009-04-01 22:02:20 -0500158 */
Dirk Behmebb732be2009-01-28 21:39:58 +0100159int misc_init_r(void)
160{
Derald D. Woods1b01bf92017-08-06 00:00:21 -0500161 twl4030_power_init();
Derald D. Woods08c291a2022-05-15 22:25:03 -0500162 twl4030_power_mmc_init(0);
Dirk Behmebb732be2009-01-28 21:39:58 +0100163
Derald D. Woods9aa45bc2020-07-18 19:23:04 -0500164#if defined(CONFIG_SMC911X)
Dirk Behmebb732be2009-01-28 21:39:58 +0100165 setup_net_chip();
166#endif
Sanjeev Premi88105fb2010-11-04 16:02:32 -0400167 omap3_evm_get_revision();
Dirk Behmebb732be2009-01-28 21:39:58 +0100168
Derald D. Woods9aa45bc2020-07-18 19:23:04 -0500169#if defined(CONFIG_SMC911X)
Sanjeev Premi5e09e442011-07-18 09:20:15 -0400170 reset_net_chip();
171#endif
Paul Kocialkowski6bc318e2015-08-27 19:37:13 +0200172 omap_die_id_display();
Dirk Behme12dbcf62009-03-12 19:30:50 +0100173
Derald D. Woods9aa45bc2020-07-18 19:23:04 -0500174#if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && \
175 !defined(CONFIG_SMC911X)
Derald D. Woods1b01bf92017-08-06 00:00:21 -0500176 omap_die_id_usbethaddr();
177#endif
Dirk Behmebb732be2009-01-28 21:39:58 +0100178 return 0;
179}
180
Tom Rix558bb832009-04-01 22:02:20 -0500181/*
Dirk Behmebb732be2009-01-28 21:39:58 +0100182 * Routine: set_muxconf_regs
183 * Description: Setting up the configuration Mux registers specific to the
184 * hardware. Many pins need to be moved from protect to primary
185 * mode.
Tom Rix558bb832009-04-01 22:02:20 -0500186 */
Dirk Behmebb732be2009-01-28 21:39:58 +0100187void set_muxconf_regs(void)
188{
189 MUX_EVM();
190}
191
Derald D. Woods9aa45bc2020-07-18 19:23:04 -0500192#if defined(CONFIG_SMC911X)
Tom Rix558bb832009-04-01 22:02:20 -0500193/*
Dirk Behmebb732be2009-01-28 21:39:58 +0100194 * Routine: setup_net_chip
195 * Description: Setting up the configuration GPMC registers specific to the
196 * Ethernet hardware.
Tom Rix558bb832009-04-01 22:02:20 -0500197 */
Dirk Behmebb732be2009-01-28 21:39:58 +0100198static void setup_net_chip(void)
199{
Dirk Behmedc7af202009-08-08 09:30:21 +0200200 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
Dirk Behmebb732be2009-01-28 21:39:58 +0100201
202 /* Configure GPMC registers */
Dirk Behmea4becd62009-08-08 09:30:22 +0200203 writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
204 writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
205 writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
206 writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
207 writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
208 writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
209 writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
Dirk Behmebb732be2009-01-28 21:39:58 +0100210
211 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
212 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
213 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
214 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
215 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
216 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
217 &ctrl_base->gpmc_nadv_ale);
Sanjeev Premi5e09e442011-07-18 09:20:15 -0400218}
219
220/**
221 * Reset the ethernet chip.
222 */
223static void reset_net_chip(void)
224{
Sriramakrishnan0f188c32011-07-18 09:21:55 -0400225 int ret;
226 int rst_gpio;
227
228 if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
229 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
230 } else {
231 rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
232 }
Dirk Behmebb732be2009-01-28 21:39:58 +0100233
Sanjeev Premi7b3dc822011-09-08 10:51:01 -0400234 ret = gpio_request(rst_gpio, "");
Sriramakrishnan0f188c32011-07-18 09:21:55 -0400235 if (ret < 0) {
236 printf("Unable to get GPIO %d\n", rst_gpio);
Bin Meng75a6a372022-10-26 12:40:07 +0800237 return;
Sriramakrishnan0f188c32011-07-18 09:21:55 -0400238 }
Dirk Behmebb732be2009-01-28 21:39:58 +0100239
Sriramakrishnan0f188c32011-07-18 09:21:55 -0400240 /* Configure as output */
Sanjeev Premi7b3dc822011-09-08 10:51:01 -0400241 gpio_direction_output(rst_gpio, 0);
Sriramakrishnan0f188c32011-07-18 09:21:55 -0400242
243 /* Send a pulse on the GPIO pin */
Sanjeev Premi7b3dc822011-09-08 10:51:01 -0400244 gpio_set_value(rst_gpio, 1);
Dirk Behmebb732be2009-01-28 21:39:58 +0100245 udelay(1);
Sanjeev Premi7b3dc822011-09-08 10:51:01 -0400246 gpio_set_value(rst_gpio, 0);
Dirk Behmebb732be2009-01-28 21:39:58 +0100247 udelay(1);
Sanjeev Premi7b3dc822011-09-08 10:51:01 -0400248 gpio_set_value(rst_gpio, 1);
Dirk Behmebb732be2009-01-28 21:39:58 +0100249}
Derald D. Woods9aa45bc2020-07-18 19:23:04 -0500250#endif /* CONFIG_SMC911X */