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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese073efd72015-04-25 06:29:56 +02002/*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
Stefan Roese073efd72015-04-25 06:29:56 +02004 */
5
Tom Rini502e50f2024-04-30 20:40:57 -06006#include <config.h>
Stefan Roese073efd72015-04-25 06:29:56 +02007#include <i2c.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Stefan Roese073efd72015-04-25 06:29:56 +02009#include <miiphy.h>
Simon Glass274e0b02020-05-10 11:39:56 -060010#include <net.h>
Stefan Roesec22b7012015-08-11 12:50:58 +020011#include <netdev.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Stefan Roese073efd72015-04-25 06:29:56 +020013#include <asm/io.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/soc.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Stefan Roese073efd72015-04-25 06:29:56 +020017
Chris Packham1a07d212018-05-10 13:28:29 +120018#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
Kevin Smith0277a6b2015-10-23 17:53:19 +000019#include <../serdes/a38x/high_speed_env_spec.h>
Stefan Roese5caab192015-03-25 13:35:15 +010020
Stefan Roese073efd72015-04-25 06:29:56 +020021DECLARE_GLOBAL_DATA_PTR;
22
Stefan Roese073efd72015-04-25 06:29:56 +020023/*
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2013.01-2014_T3.0"
26 */
27#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
28 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
29 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
30 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
31#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
32 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
33 BIT(16) | BIT(17) | BIT(18)))
34
35#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
36#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
37#define DB_GP_88F68XX_GPP_POL_LOW 0x0
38#define DB_GP_88F68XX_GPP_POL_MID 0x0
39
40/* IO expander on Marvell GP board includes e.g. fan enabling */
41struct marvell_io_exp {
42 u8 chip;
43 u8 addr;
44 u8 val;
45};
46
47static struct marvell_io_exp io_exp[] = {
48 { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
49 { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
50 { 0x20, 2, 0x1D }, /* Output Data, register#0 */
51 { 0x20, 3, 0x18 }, /* Output Data, register#1 */
52 { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
53 { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
54 { 0x21, 2, 0x08 }, /* Output Data, register#0 */
55 { 0x21, 3, 0xC0 } /* Output Data, register#1 */
56};
57
Kevin Smith0277a6b2015-10-23 17:53:19 +000058static struct serdes_map board_serdes_map[] = {
59 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
60 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
61 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
62 {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
63 {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
65};
66
Kevin Smith6406d432015-10-23 17:53:19 +000067int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
Kevin Smith0277a6b2015-10-23 17:53:19 +000068{
Kevin Smith6406d432015-10-23 17:53:19 +000069 *serdes_map_array = board_serdes_map;
70 *count = ARRAY_SIZE(board_serdes_map);
Kevin Smith0277a6b2015-10-23 17:53:19 +000071 return 0;
72}
73
Stefan Roese5caab192015-03-25 13:35:15 +010074/*
75 * Define the DDR layout / topology here in the board file. This will
76 * be used by the DDR3 init code in the SPL U-Boot version to configure
77 * the DDR3 controller.
78 */
Chris Packham1a07d212018-05-10 13:28:29 +120079static struct mv_ddr_topology_map board_topology_map = {
80 DEBUG_LEVEL_ERROR,
Stefan Roese5caab192015-03-25 13:35:15 +010081 0x1, /* active interfaces */
82 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
83 { { { {0x1, 0, 0, 0},
84 {0x1, 0, 0, 0},
85 {0x1, 0, 0, 0},
86 {0x1, 0, 0, 0},
87 {0x1, 0, 0, 0} },
88 SPEED_BIN_DDR_1866L, /* speed_bin */
Chris Packham1a07d212018-05-10 13:28:29 +120089 MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
90 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
Chris Packham4bf81db2018-12-03 14:26:49 +130091 MV_DDR_FREQ_800, /* frequency */
Chris Packhamdd092bd2017-11-29 10:38:34 +130092 0, 0, /* cas_wl cas_l */
Chris Packham3a09e132018-05-10 13:28:30 +120093 MV_DDR_TEMP_LOW, /* temperature */
94 MV_DDR_TIM_DEFAULT} }, /* timing */
Chris Packham1a07d212018-05-10 13:28:29 +120095 BUS_MASK_32BIT, /* Busses mask */
96 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
Moti Buskila498475e2021-02-19 17:11:19 +010097 NOT_COMBINED, /* ddr twin-die combined */
Chris Packham1a07d212018-05-10 13:28:29 +120098 { {0} }, /* raw spd data */
99 {0} /* timing parameters */
Stefan Roese5caab192015-03-25 13:35:15 +0100100};
101
Chris Packham1a07d212018-05-10 13:28:29 +1200102struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
Stefan Roese5caab192015-03-25 13:35:15 +0100103{
104 /* Return the board topology as defined in the board code */
105 return &board_topology_map;
106}
107
Stefan Roese073efd72015-04-25 06:29:56 +0200108int board_early_init_f(void)
109{
110 /* Configure MPP */
111 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
112 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
113 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
114 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
115 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
116 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
117 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
118 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
119
120 /* Set GPP Out value */
121 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
122 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
123
124 /* Set GPP Polarity */
125 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
126 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
127
128 /* Set GPP Out Enable */
129 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
130 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
131
132 return 0;
133}
134
135int board_init(void)
136{
137 int i;
138
139 /* adress of boot parameters */
140 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
141
142 /* Init I2C IO expanders */
143 for (i = 0; i < ARRAY_SIZE(io_exp); i++)
144 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
145
146 return 0;
147}
148
149int checkboard(void)
150{
151 puts("Board: Marvell DB-88F6820-GP\n");
152
153 return 0;
154}
Stefan Roesec22b7012015-08-11 12:50:58 +0200155
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +0900156int board_eth_init(struct bd_info *bis)
Stefan Roesec22b7012015-08-11 12:50:58 +0200157{
158 cpu_eth_init(bis); /* Built in controller(s) come first */
159 return pci_eth_init(bis);
160}