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git01.mediatek.com / filogic / uboot / e44b911b9c1a2e384f52cb9e7e82306a4a0b58ea / . / include / mpc5xxx.h
blob: fb0e41a34da922657cb198d81a4574bacbaf24d4 [file] [log] [blame]
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
42
wdenkeb20ad32003-09-05 23:19:14 +0000[diff] [blame]43/* useful macros for manipulating CSx_START/STOP */
44#if defined(CONFIG_MGT5100)
45#define START_REG(start) ((start) >> 15)
46#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
47#elif defined(CONFIG_MPC5200)
48#define START_REG(start) ((start) >> 16)
49#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
50#endif
51
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]52/* Internal memory map */
53
54#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
55#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
56#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
57#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
58#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
59#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
60#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
61#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
62#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
63#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
64#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
65#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
66#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
67#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
68#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
69
70#if defined(CONFIG_MGT5100)
71#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
72#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]73#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
74#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
75#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
76#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]77#elif defined(CONFIG_MPC5200)
78#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
79#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
80#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
81#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
82#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
83#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
84#endif
85
86#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
87#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
88#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
89#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]90#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]91#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]92#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]93#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
wdenk5f495752004-02-26 23:46:20 +0000[diff] [blame]94#define MPC5XXX_USB (CFG_MBAR + 0x1000)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]95#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
96#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
97
98#if defined(CONFIG_MGT5100)
99#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
100#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
101#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
102#elif defined(CONFIG_MPC5200)
103#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
104#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
105#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
106#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
107#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
108#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
109#endif
110
111#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]112#define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]113
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]114#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
115#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
116
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]117#if defined(CONFIG_MGT5100)
118#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
119#define MPC5XXX_SRAM_SIZE (8*1024)
120#elif defined(CONFIG_MPC5200)
121#define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
122#define MPC5XXX_SRAM_SIZE (16*1024)
123#endif
124
125/* SDRAM Controller */
126#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
127#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
128#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
129#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
130#if defined(CONFIG_MGT5100)
131#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
132#endif
133
134/* Clock Distribution Module */
135#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
136#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
137#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
wdenk5f495752004-02-26 23:46:20 +0000[diff] [blame]138#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]139#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
140
141/* Local Plus Bus interface */
142#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
143#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
144#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
145#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
146#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
147#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
148#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
149#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
150#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
151#if defined(CONFIG_MPC5200)
152#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
153#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
154#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
155#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
156#endif
157
wdenkf5547d32003-09-16 17:06:05 +0000[diff] [blame]158#if defined(CONFIG_MPC5200)
159/* XLB Arbiter registers */
160#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40)
161#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64)
162#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68)
163#endif
164
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]165/* GPIO registers */
166#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
167
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]168/* WakeUp GPIO registers */
169#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
170#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
171#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
172#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
173
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]174/* PCI registers */
175#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
176#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
177#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
178#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
179#if defined(CONFIG_MGT5100)
180#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
181#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
182#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
183#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
184#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
185#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
186#elif defined(CONFIG_MPC5200)
187#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
188#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
189#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
190#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
191#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
192#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
193#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
194#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
195#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
196#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
197#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
198#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
199#endif
200
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]201/* Interrupt Controller registers */
202#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
203#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
204#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
205#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
206#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
207#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
208#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
209#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
210#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
211#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
212#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
213#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
214#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
215
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]216/* General Purpose Timers registers */
217#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
218#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
219
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]220/* ATA registers */
221#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
222#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
223#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
224#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
225
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]226/* I2Cn control register bits */
227#define I2C_EN 0x80
228#define I2C_IEN 0x40
229#define I2C_STA 0x20
230#define I2C_TX 0x10
231#define I2C_TXAK 0x08
232#define I2C_RSTA 0x04
233#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
234
235/* I2Cn status register bits */
236#define I2C_CF 0x80
237#define I2C_AAS 0x40
238#define I2C_BB 0x20
239#define I2C_AL 0x10
240#define I2C_SRW 0x04
241#define I2C_IF 0x02
242#define I2C_RXAK 0x01
243
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]244/* Programmable Serial Controller (PSC) status register bits */
245#define PSC_SR_CDE 0x0080
246#define PSC_SR_RXRDY 0x0100
247#define PSC_SR_RXFULL 0x0200
248#define PSC_SR_TXRDY 0x0400
249#define PSC_SR_TXEMP 0x0800
250#define PSC_SR_OE 0x1000
251#define PSC_SR_PE 0x2000
252#define PSC_SR_FE 0x4000
253#define PSC_SR_RB 0x8000
254
255/* PSC Command values */
256#define PSC_RX_ENABLE 0x0001
257#define PSC_RX_DISABLE 0x0002
258#define PSC_TX_ENABLE 0x0004
259#define PSC_TX_DISABLE 0x0008
260#define PSC_SEL_MODE_REG_1 0x0010
261#define PSC_RST_RX 0x0020
262#define PSC_RST_TX 0x0030
263#define PSC_RST_ERR_STAT 0x0040
264#define PSC_RST_BRK_CHG_INT 0x0050
265#define PSC_START_BRK 0x0060
266#define PSC_STOP_BRK 0x0070
267
268/* PSC Rx FIFO status bits */
269#define PSC_RX_FIFO_ERR 0x0040
270#define PSC_RX_FIFO_UF 0x0020
271#define PSC_RX_FIFO_OF 0x0010
272#define PSC_RX_FIFO_FR 0x0008
273#define PSC_RX_FIFO_FULL 0x0004
274#define PSC_RX_FIFO_ALARM 0x0002
275#define PSC_RX_FIFO_EMPTY 0x0001
276
277/* PSC interrupt mask bits */
278#define PSC_IMR_TXRDY 0x0100
279#define PSC_IMR_RXRDY 0x0200
280#define PSC_IMR_DB 0x0400
281#define PSC_IMR_IPC 0x8000
282
283/* PSC input port change bits */
284#define PSC_IPCR_CTS 0x01
285#define PSC_IPCR_DCD 0x02
286
287/* PSC mode fields */
288#define PSC_MODE_5_BITS 0x00
289#define PSC_MODE_6_BITS 0x01
290#define PSC_MODE_7_BITS 0x02
291#define PSC_MODE_8_BITS 0x03
292#define PSC_MODE_PAREVEN 0x00
293#define PSC_MODE_PARODD 0x04
294#define PSC_MODE_PARFORCE 0x08
295#define PSC_MODE_PARNONE 0x10
296#define PSC_MODE_ERR 0x20
297#define PSC_MODE_FFULL 0x40
298#define PSC_MODE_RXRTS 0x80
299
300#define PSC_MODE_ONE_STOP_5_BITS 0x00
301#define PSC_MODE_ONE_STOP 0x07
302#define PSC_MODE_TWO_STOP 0x0f
303
wdenk6ea1cf02004-02-27 08:20:54 +0000[diff] [blame]304/* ATA config fields */
305#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
306 reset */
307#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
308#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
309 in PIO */
310#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
311 IORDY protocol */
312
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]313#ifndef __ASSEMBLY__
314struct mpc5xxx_psc {
315 volatile u8 mode; /* PSC + 0x00 */
316 volatile u8 reserved0[3];
317 union { /* PSC + 0x04 */
318 volatile u16 status;
319 volatile u16 clock_select;
320 } sr_csr;
321#define psc_status sr_csr.status
322#define psc_clock_select sr_csr.clock_select
323 volatile u16 reserved1;
324 volatile u8 command; /* PSC + 0x08 */
325 volatile u8 reserved2[3];
326 union { /* PSC + 0x0c */
327 volatile u8 buffer_8;
328 volatile u16 buffer_16;
329 volatile u32 buffer_32;
330 } buffer;
331#define psc_buffer_8 buffer.buffer_8
332#define psc_buffer_16 buffer.buffer_16
333#define psc_buffer_32 buffer.buffer_32
334 union { /* PSC + 0x10 */
335 volatile u8 ipcr;
336 volatile u8 acr;
337 } ipcr_acr;
338#define psc_ipcr ipcr_acr.ipcr
339#define psc_acr ipcr_acr.acr
340 volatile u8 reserved3[3];
341 union { /* PSC + 0x14 */
342 volatile u16 isr;
343 volatile u16 imr;
344 } isr_imr;
345#define psc_isr isr_imr.isr
346#define psc_imr isr_imr.imr
347 volatile u16 reserved4;
348 volatile u8 ctur; /* PSC + 0x18 */
349 volatile u8 reserved5[3];
350 volatile u8 ctlr; /* PSC + 0x1c */
351 volatile u8 reserved6[19];
352 volatile u8 ivr; /* PSC + 0x30 */
353 volatile u8 reserved7[3];
354 volatile u8 ip; /* PSC + 0x34 */
355 volatile u8 reserved8[3];
356 volatile u8 op1; /* PSC + 0x38 */
357 volatile u8 reserved9[3];
358 volatile u8 op0; /* PSC + 0x3c */
359 volatile u8 reserved10[3];
360 volatile u8 sicr; /* PSC + 0x40 */
361 volatile u8 reserved11[3];
362 volatile u8 ircr1; /* PSC + 0x44 */
363 volatile u8 reserved12[3];
364 volatile u8 ircr2; /* PSC + 0x44 */
365 volatile u8 reserved13[3];
366 volatile u8 irsdr; /* PSC + 0x4c */
367 volatile u8 reserved14[3];
368 volatile u8 irmdr; /* PSC + 0x50 */
369 volatile u8 reserved15[3];
370 volatile u8 irfdr; /* PSC + 0x54 */
371 volatile u8 reserved16[3];
372 volatile u16 rfnum; /* PSC + 0x58 */
373 volatile u16 reserved17;
374 volatile u16 tfnum; /* PSC + 0x5c */
375 volatile u16 reserved18;
376 volatile u32 rfdata; /* PSC + 0x60 */
377 volatile u16 rfstat; /* PSC + 0x64 */
378 volatile u16 reserved20;
379 volatile u8 rfcntl; /* PSC + 0x68 */
380 volatile u8 reserved21[5];
381 volatile u16 rfalarm; /* PSC + 0x6e */
382 volatile u16 reserved22;
383 volatile u16 rfrptr; /* PSC + 0x72 */
384 volatile u16 reserved23;
385 volatile u16 rfwptr; /* PSC + 0x76 */
386 volatile u16 reserved24;
387 volatile u16 rflrfptr; /* PSC + 0x7a */
388 volatile u16 reserved25;
389 volatile u16 rflwfptr; /* PSC + 0x7e */
390 volatile u32 tfdata; /* PSC + 0x80 */
391 volatile u16 tfstat; /* PSC + 0x84 */
392 volatile u16 reserved26;
393 volatile u8 tfcntl; /* PSC + 0x88 */
394 volatile u8 reserved27[5];
395 volatile u16 tfalarm; /* PSC + 0x8e */
396 volatile u16 reserved28;
397 volatile u16 tfrptr; /* PSC + 0x92 */
398 volatile u16 reserved29;
399 volatile u16 tfwptr; /* PSC + 0x96 */
400 volatile u16 reserved30;
401 volatile u16 tflrfptr; /* PSC + 0x9a */
402 volatile u16 reserved31;
403 volatile u16 tflwfptr; /* PSC + 0x9e */
404};
405
406struct mpc5xxx_intr {
407 volatile u32 per_mask; /* INTR + 0x00 */
408 volatile u32 per_pri1; /* INTR + 0x04 */
409 volatile u32 per_pri2; /* INTR + 0x08 */
410 volatile u32 per_pri3; /* INTR + 0x0c */
411 volatile u32 ctrl; /* INTR + 0x10 */
412 volatile u32 main_mask; /* INTR + 0x14 */
413 volatile u32 main_pri1; /* INTR + 0x18 */
414 volatile u32 main_pri2; /* INTR + 0x1c */
415 volatile u32 reserved1; /* INTR + 0x20 */
416 volatile u32 enc_status; /* INTR + 0x24 */
417 volatile u32 crit_status; /* INTR + 0x28 */
418 volatile u32 main_status; /* INTR + 0x2c */
419 volatile u32 per_status; /* INTR + 0x30 */
420 volatile u32 reserved2; /* INTR + 0x34 */
421 volatile u32 per_error; /* INTR + 0x38 */
422};
423
424struct mpc5xxx_gpio {
425 volatile u32 port_config; /* GPIO + 0x00 */
426 volatile u32 simple_gpioe; /* GPIO + 0x04 */
427 volatile u32 simple_ode; /* GPIO + 0x08 */
428 volatile u32 simple_ddr; /* GPIO + 0x0c */
429 volatile u32 simple_dvo; /* GPIO + 0x10 */
430 volatile u32 simple_ival; /* GPIO + 0x14 */
431 volatile u8 outo_gpioe; /* GPIO + 0x18 */
432 volatile u8 reserved1[3]; /* GPIO + 0x19 */
433 volatile u8 outo_dvo; /* GPIO + 0x1c */
434 volatile u8 reserved2[3]; /* GPIO + 0x1d */
435 volatile u8 sint_gpioe; /* GPIO + 0x20 */
436 volatile u8 reserved3[3]; /* GPIO + 0x21 */
437 volatile u8 sint_ode; /* GPIO + 0x24 */
438 volatile u8 reserved4[3]; /* GPIO + 0x25 */
439 volatile u8 sint_ddr; /* GPIO + 0x28 */
440 volatile u8 reserved5[3]; /* GPIO + 0x29 */
441 volatile u8 sint_dvo; /* GPIO + 0x2c */
442 volatile u8 reserved6[3]; /* GPIO + 0x2d */
443 volatile u8 sint_inten; /* GPIO + 0x30 */
444 volatile u8 reserved7[3]; /* GPIO + 0x31 */
445 volatile u16 sint_itype; /* GPIO + 0x34 */
446 volatile u16 reserved8; /* GPIO + 0x36 */
447 volatile u8 gpio_control; /* GPIO + 0x38 */
448 volatile u8 reserved9[3]; /* GPIO + 0x39 */
449 volatile u8 sint_istat; /* GPIO + 0x3c */
450 volatile u8 sint_ival; /* GPIO + 0x3d */
451 volatile u8 bus_errs; /* GPIO + 0x3e */
452 volatile u8 reserved10; /* GPIO + 0x3f */
453};
454
455struct mpc5xxx_sdma {
456 volatile u32 taskBar; /* SDMA + 0x00 */
457 volatile u32 currentPointer; /* SDMA + 0x04 */
458 volatile u32 endPointer; /* SDMA + 0x08 */
459 volatile u32 variablePointer; /* SDMA + 0x0c */
460
461 volatile u8 IntVect1; /* SDMA + 0x10 */
462 volatile u8 IntVect2; /* SDMA + 0x11 */
463 volatile u16 PtdCntrl; /* SDMA + 0x12 */
464
465 volatile u32 IntPend; /* SDMA + 0x14 */
466 volatile u32 IntMask; /* SDMA + 0x18 */
467
468 volatile u16 tcr_0; /* SDMA + 0x1c */
469 volatile u16 tcr_1; /* SDMA + 0x1e */
470 volatile u16 tcr_2; /* SDMA + 0x20 */
471 volatile u16 tcr_3; /* SDMA + 0x22 */
472 volatile u16 tcr_4; /* SDMA + 0x24 */
473 volatile u16 tcr_5; /* SDMA + 0x26 */
474 volatile u16 tcr_6; /* SDMA + 0x28 */
475 volatile u16 tcr_7; /* SDMA + 0x2a */
476 volatile u16 tcr_8; /* SDMA + 0x2c */
477 volatile u16 tcr_9; /* SDMA + 0x2e */
478 volatile u16 tcr_a; /* SDMA + 0x30 */
479 volatile u16 tcr_b; /* SDMA + 0x32 */
480 volatile u16 tcr_c; /* SDMA + 0x34 */
481 volatile u16 tcr_d; /* SDMA + 0x36 */
482 volatile u16 tcr_e; /* SDMA + 0x38 */
483 volatile u16 tcr_f; /* SDMA + 0x3a */
484
485 volatile u8 IPR0; /* SDMA + 0x3c */
486 volatile u8 IPR1; /* SDMA + 0x3d */
487 volatile u8 IPR2; /* SDMA + 0x3e */
488 volatile u8 IPR3; /* SDMA + 0x3f */
489 volatile u8 IPR4; /* SDMA + 0x40 */
490 volatile u8 IPR5; /* SDMA + 0x41 */
491 volatile u8 IPR6; /* SDMA + 0x42 */
492 volatile u8 IPR7; /* SDMA + 0x43 */
493 volatile u8 IPR8; /* SDMA + 0x44 */
494 volatile u8 IPR9; /* SDMA + 0x45 */
495 volatile u8 IPR10; /* SDMA + 0x46 */
496 volatile u8 IPR11; /* SDMA + 0x47 */
497 volatile u8 IPR12; /* SDMA + 0x48 */
498 volatile u8 IPR13; /* SDMA + 0x49 */
499 volatile u8 IPR14; /* SDMA + 0x4a */
500 volatile u8 IPR15; /* SDMA + 0x4b */
501 volatile u8 IPR16; /* SDMA + 0x4c */
502 volatile u8 IPR17; /* SDMA + 0x4d */
503 volatile u8 IPR18; /* SDMA + 0x4e */
504 volatile u8 IPR19; /* SDMA + 0x4f */
505 volatile u8 IPR20; /* SDMA + 0x50 */
506 volatile u8 IPR21; /* SDMA + 0x51 */
507 volatile u8 IPR22; /* SDMA + 0x52 */
508 volatile u8 IPR23; /* SDMA + 0x53 */
509 volatile u8 IPR24; /* SDMA + 0x54 */
510 volatile u8 IPR25; /* SDMA + 0x55 */
511 volatile u8 IPR26; /* SDMA + 0x56 */
512 volatile u8 IPR27; /* SDMA + 0x57 */
513 volatile u8 IPR28; /* SDMA + 0x58 */
514 volatile u8 IPR29; /* SDMA + 0x59 */
515 volatile u8 IPR30; /* SDMA + 0x5a */
516 volatile u8 IPR31; /* SDMA + 0x5b */
517
518 volatile u32 res1; /* SDMA + 0x5c */
519 volatile u32 res2; /* SDMA + 0x60 */
520 volatile u32 res3; /* SDMA + 0x64 */
521 volatile u32 MDEDebug; /* SDMA + 0x68 */
522 volatile u32 ADSDebug; /* SDMA + 0x6c */
523 volatile u32 Value1; /* SDMA + 0x70 */
524 volatile u32 Value2; /* SDMA + 0x74 */
525 volatile u32 Control; /* SDMA + 0x78 */
526 volatile u32 Status; /* SDMA + 0x7c */
527 volatile u32 EU00; /* SDMA + 0x80 */
528 volatile u32 EU01; /* SDMA + 0x84 */
529 volatile u32 EU02; /* SDMA + 0x88 */
530 volatile u32 EU03; /* SDMA + 0x8c */
531 volatile u32 EU04; /* SDMA + 0x90 */
532 volatile u32 EU05; /* SDMA + 0x94 */
533 volatile u32 EU06; /* SDMA + 0x98 */
534 volatile u32 EU07; /* SDMA + 0x9c */
535 volatile u32 EU10; /* SDMA + 0xa0 */
536 volatile u32 EU11; /* SDMA + 0xa4 */
537 volatile u32 EU12; /* SDMA + 0xa8 */
538 volatile u32 EU13; /* SDMA + 0xac */
539 volatile u32 EU14; /* SDMA + 0xb0 */
540 volatile u32 EU15; /* SDMA + 0xb4 */
541 volatile u32 EU16; /* SDMA + 0xb8 */
542 volatile u32 EU17; /* SDMA + 0xbc */
543 volatile u32 EU20; /* SDMA + 0xc0 */
544 volatile u32 EU21; /* SDMA + 0xc4 */
545 volatile u32 EU22; /* SDMA + 0xc8 */
546 volatile u32 EU23; /* SDMA + 0xcc */
547 volatile u32 EU24; /* SDMA + 0xd0 */
548 volatile u32 EU25; /* SDMA + 0xd4 */
549 volatile u32 EU26; /* SDMA + 0xd8 */
550 volatile u32 EU27; /* SDMA + 0xdc */
551 volatile u32 EU30; /* SDMA + 0xe0 */
552 volatile u32 EU31; /* SDMA + 0xe4 */
553 volatile u32 EU32; /* SDMA + 0xe8 */
554 volatile u32 EU33; /* SDMA + 0xec */
555 volatile u32 EU34; /* SDMA + 0xf0 */
556 volatile u32 EU35; /* SDMA + 0xf4 */
557 volatile u32 EU36; /* SDMA + 0xf8 */
558 volatile u32 EU37; /* SDMA + 0xfc */
559};
560
wdenk25521902003-09-13 19:01:12 +0000[diff] [blame]561struct mpc5xxx_i2c {
562 volatile u32 madr; /* I2Cn + 0x00 */
563 volatile u32 mfdr; /* I2Cn + 0x04 */
564 volatile u32 mcr; /* I2Cn + 0x08 */
565 volatile u32 msr; /* I2Cn + 0x0C */
566 volatile u32 mdr; /* I2Cn + 0x10 */
567};
568
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]569/* function prototypes */
570void loadtask(int basetask, int tasks);
571
572#endif /* __ASSEMBLY__ */
573
574#endif /* __ASMPPC_MPC5XXX_H */