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git01.mediatek.com / filogic / uboot / eb20ad3d1e6f42af2ad50fbfeca5ba448f1266f7 / . / include / mpc5xxx.h
blob: 02683e3820804a4a905d9f1496e632f4ece08349 [file] [log] [blame]
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]1/*
2 * include/asm-ppc/mpc5xxx.h
3 *
4 * Prototypes, etc. for the Motorola MGT5xxx/MPC5xxx
5 * embedded cpu chips
6 *
7 * 2003 (c) MontaVista, Software, Inc.
8 * Author: Dale Farnsworth <dfarnsworth@mvista.com>
9 *
10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30#ifndef __ASMPPC_MPC5XXX_H
31#define __ASMPPC_MPC5XXX_H
32
33/* Processor name */
34#if defined(CONFIG_MPC5200)
35#define CPU_ID_STR "MPC5200"
36#elif defined(CONFIG_MGT5100)
37#define CPU_ID_STR "MGT5100"
38#endif
39
40/* Exception offsets (PowerPC standard) */
41#define EXC_OFF_SYS_RESET 0x0100
42
wdenkeb20ad32003-09-05 23:19:14 +0000[diff] [blame^]43/* useful macros for manipulating CSx_START/STOP */
44#if defined(CONFIG_MGT5100)
45#define START_REG(start) ((start) >> 15)
46#define STOP_REG(start, size) (((start) + (size) - 1) >> 15)
47#elif defined(CONFIG_MPC5200)
48#define START_REG(start) ((start) >> 16)
49#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
50#endif
51
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]52/* Internal memory map */
53
54#define MPC5XXX_CS0_START (CFG_MBAR + 0x0004)
55#define MPC5XXX_CS0_STOP (CFG_MBAR + 0x0008)
56#define MPC5XXX_CS1_START (CFG_MBAR + 0x000c)
57#define MPC5XXX_CS1_STOP (CFG_MBAR + 0x0010)
58#define MPC5XXX_CS2_START (CFG_MBAR + 0x0014)
59#define MPC5XXX_CS2_STOP (CFG_MBAR + 0x0018)
60#define MPC5XXX_CS3_START (CFG_MBAR + 0x001c)
61#define MPC5XXX_CS3_STOP (CFG_MBAR + 0x0020)
62#define MPC5XXX_CS4_START (CFG_MBAR + 0x0024)
63#define MPC5XXX_CS4_STOP (CFG_MBAR + 0x0028)
64#define MPC5XXX_CS5_START (CFG_MBAR + 0x002c)
65#define MPC5XXX_CS5_STOP (CFG_MBAR + 0x0030)
66#define MPC5XXX_BOOTCS_START (CFG_MBAR + 0x004c)
67#define MPC5XXX_BOOTCS_STOP (CFG_MBAR + 0x0050)
68#define MPC5XXX_ADDECR (CFG_MBAR + 0x0054)
69
70#if defined(CONFIG_MGT5100)
71#define MPC5XXX_SDRAM_START (CFG_MBAR + 0x0034)
72#define MPC5XXX_SDRAM_STOP (CFG_MBAR + 0x0038)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]73#define MPC5XXX_PCI1_START (CFG_MBAR + 0x003c)
74#define MPC5XXX_PCI1_STOP (CFG_MBAR + 0x0040)
75#define MPC5XXX_PCI2_START (CFG_MBAR + 0x0044)
76#define MPC5XXX_PCI2_STOP (CFG_MBAR + 0x0048)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]77#elif defined(CONFIG_MPC5200)
78#define MPC5XXX_CS6_START (CFG_MBAR + 0x0058)
79#define MPC5XXX_CS6_STOP (CFG_MBAR + 0x005c)
80#define MPC5XXX_CS7_START (CFG_MBAR + 0x0060)
81#define MPC5XXX_CS7_STOP (CFG_MBAR + 0x0064)
82#define MPC5XXX_SDRAM_CS0CFG (CFG_MBAR + 0x0034)
83#define MPC5XXX_SDRAM_CS1CFG (CFG_MBAR + 0x0038)
84#endif
85
86#define MPC5XXX_SDRAM (CFG_MBAR + 0x0100)
87#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
88#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
89#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]90#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]91#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]92#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]93#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
94#define MPC5XXX_XLBARB (CFG_MBAR + 0x1f00)
95
96#if defined(CONFIG_MGT5100)
97#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
98#define MPC5XXX_PSC2 (CFG_MBAR + 0x2400)
99#define MPC5XXX_PSC3 (CFG_MBAR + 0x2800)
100#elif defined(CONFIG_MPC5200)
101#define MPC5XXX_PSC1 (CFG_MBAR + 0x2000)
102#define MPC5XXX_PSC2 (CFG_MBAR + 0x2200)
103#define MPC5XXX_PSC3 (CFG_MBAR + 0x2400)
104#define MPC5XXX_PSC4 (CFG_MBAR + 0x2600)
105#define MPC5XXX_PSC5 (CFG_MBAR + 0x2800)
106#define MPC5XXX_PSC6 (CFG_MBAR + 0x2c00)
107#endif
108
109#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
110
111#if defined(CONFIG_MGT5100)
112#define MPC5XXX_SRAM (CFG_MBAR + 0x4000)
113#define MPC5XXX_SRAM_SIZE (8*1024)
114#elif defined(CONFIG_MPC5200)
115#define MPC5XXX_SRAM (CFG_MBAR + 0x8000)
116#define MPC5XXX_SRAM_SIZE (16*1024)
117#endif
118
119/* SDRAM Controller */
120#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000)
121#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004)
122#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008)
123#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c)
124#if defined(CONFIG_MGT5100)
125#define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010)
126#endif
127
128/* Clock Distribution Module */
129#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000)
130#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004)
131#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c)
132#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020)
133
134/* Local Plus Bus interface */
135#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000)
136#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004)
137#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008)
138#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c)
139#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010)
140#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014)
141#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG
142#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018)
143#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c)
144#if defined(CONFIG_MPC5200)
145#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020)
146#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024)
147#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028)
148#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c)
149#endif
150
151/* GPIO registers */
152#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
153
wdenk02379022003-08-05 18:22:44 +0000[diff] [blame]154/* PCI registers */
155#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
156#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
157#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10)
158#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14)
159#if defined(CONFIG_MGT5100)
160#define MPC5XXX_PCI_CTRL (MPC5XXX_PCI + 0x68)
161#define MPC5XXX_PCI_VALMSKR (MPC5XXX_PCI + 0x6c)
162#define MPC5XXX_PCI_VALMSKW (MPC5XXX_PCI + 0x70)
163#define MPC5XXX_PCI_SUBW1 (MPC5XXX_PCI + 0x74)
164#define MPC5XXX_PCI_SUBW2 (MPC5XXX_PCI + 0x78)
165#define MPC5XXX_PCI_WINCOMMAND (MPC5XXX_PCI + 0x7c)
166#elif defined(CONFIG_MPC5200)
167#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60)
168#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64)
169#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68)
170#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c)
171#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70)
172#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74)
173#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78)
174#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80)
175#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84)
176#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88)
177#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c)
178#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8)
179#endif
180
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]181/* Interrupt Controller registers */
182#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000)
183#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004)
184#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008)
185#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c)
186#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010)
187#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014)
188#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018)
189#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c)
190#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024)
191#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028)
192#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
193#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
194#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
195
wdenkb10ba6b2003-08-28 09:41:22 +0000[diff] [blame]196/* General Purpose Timers registers */
197#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
198#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
199
wdenk21136db2003-07-16 21:53:01 +0000[diff] [blame]200/* Programmable Serial Controller (PSC) status register bits */
201#define PSC_SR_CDE 0x0080
202#define PSC_SR_RXRDY 0x0100
203#define PSC_SR_RXFULL 0x0200
204#define PSC_SR_TXRDY 0x0400
205#define PSC_SR_TXEMP 0x0800
206#define PSC_SR_OE 0x1000
207#define PSC_SR_PE 0x2000
208#define PSC_SR_FE 0x4000
209#define PSC_SR_RB 0x8000
210
211/* PSC Command values */
212#define PSC_RX_ENABLE 0x0001
213#define PSC_RX_DISABLE 0x0002
214#define PSC_TX_ENABLE 0x0004
215#define PSC_TX_DISABLE 0x0008
216#define PSC_SEL_MODE_REG_1 0x0010
217#define PSC_RST_RX 0x0020
218#define PSC_RST_TX 0x0030
219#define PSC_RST_ERR_STAT 0x0040
220#define PSC_RST_BRK_CHG_INT 0x0050
221#define PSC_START_BRK 0x0060
222#define PSC_STOP_BRK 0x0070
223
224/* PSC Rx FIFO status bits */
225#define PSC_RX_FIFO_ERR 0x0040
226#define PSC_RX_FIFO_UF 0x0020
227#define PSC_RX_FIFO_OF 0x0010
228#define PSC_RX_FIFO_FR 0x0008
229#define PSC_RX_FIFO_FULL 0x0004
230#define PSC_RX_FIFO_ALARM 0x0002
231#define PSC_RX_FIFO_EMPTY 0x0001
232
233/* PSC interrupt mask bits */
234#define PSC_IMR_TXRDY 0x0100
235#define PSC_IMR_RXRDY 0x0200
236#define PSC_IMR_DB 0x0400
237#define PSC_IMR_IPC 0x8000
238
239/* PSC input port change bits */
240#define PSC_IPCR_CTS 0x01
241#define PSC_IPCR_DCD 0x02
242
243/* PSC mode fields */
244#define PSC_MODE_5_BITS 0x00
245#define PSC_MODE_6_BITS 0x01
246#define PSC_MODE_7_BITS 0x02
247#define PSC_MODE_8_BITS 0x03
248#define PSC_MODE_PAREVEN 0x00
249#define PSC_MODE_PARODD 0x04
250#define PSC_MODE_PARFORCE 0x08
251#define PSC_MODE_PARNONE 0x10
252#define PSC_MODE_ERR 0x20
253#define PSC_MODE_FFULL 0x40
254#define PSC_MODE_RXRTS 0x80
255
256#define PSC_MODE_ONE_STOP_5_BITS 0x00
257#define PSC_MODE_ONE_STOP 0x07
258#define PSC_MODE_TWO_STOP 0x0f
259
260#ifndef __ASSEMBLY__
261struct mpc5xxx_psc {
262 volatile u8 mode; /* PSC + 0x00 */
263 volatile u8 reserved0[3];
264 union { /* PSC + 0x04 */
265 volatile u16 status;
266 volatile u16 clock_select;
267 } sr_csr;
268#define psc_status sr_csr.status
269#define psc_clock_select sr_csr.clock_select
270 volatile u16 reserved1;
271 volatile u8 command; /* PSC + 0x08 */
272 volatile u8 reserved2[3];
273 union { /* PSC + 0x0c */
274 volatile u8 buffer_8;
275 volatile u16 buffer_16;
276 volatile u32 buffer_32;
277 } buffer;
278#define psc_buffer_8 buffer.buffer_8
279#define psc_buffer_16 buffer.buffer_16
280#define psc_buffer_32 buffer.buffer_32
281 union { /* PSC + 0x10 */
282 volatile u8 ipcr;
283 volatile u8 acr;
284 } ipcr_acr;
285#define psc_ipcr ipcr_acr.ipcr
286#define psc_acr ipcr_acr.acr
287 volatile u8 reserved3[3];
288 union { /* PSC + 0x14 */
289 volatile u16 isr;
290 volatile u16 imr;
291 } isr_imr;
292#define psc_isr isr_imr.isr
293#define psc_imr isr_imr.imr
294 volatile u16 reserved4;
295 volatile u8 ctur; /* PSC + 0x18 */
296 volatile u8 reserved5[3];
297 volatile u8 ctlr; /* PSC + 0x1c */
298 volatile u8 reserved6[19];
299 volatile u8 ivr; /* PSC + 0x30 */
300 volatile u8 reserved7[3];
301 volatile u8 ip; /* PSC + 0x34 */
302 volatile u8 reserved8[3];
303 volatile u8 op1; /* PSC + 0x38 */
304 volatile u8 reserved9[3];
305 volatile u8 op0; /* PSC + 0x3c */
306 volatile u8 reserved10[3];
307 volatile u8 sicr; /* PSC + 0x40 */
308 volatile u8 reserved11[3];
309 volatile u8 ircr1; /* PSC + 0x44 */
310 volatile u8 reserved12[3];
311 volatile u8 ircr2; /* PSC + 0x44 */
312 volatile u8 reserved13[3];
313 volatile u8 irsdr; /* PSC + 0x4c */
314 volatile u8 reserved14[3];
315 volatile u8 irmdr; /* PSC + 0x50 */
316 volatile u8 reserved15[3];
317 volatile u8 irfdr; /* PSC + 0x54 */
318 volatile u8 reserved16[3];
319 volatile u16 rfnum; /* PSC + 0x58 */
320 volatile u16 reserved17;
321 volatile u16 tfnum; /* PSC + 0x5c */
322 volatile u16 reserved18;
323 volatile u32 rfdata; /* PSC + 0x60 */
324 volatile u16 rfstat; /* PSC + 0x64 */
325 volatile u16 reserved20;
326 volatile u8 rfcntl; /* PSC + 0x68 */
327 volatile u8 reserved21[5];
328 volatile u16 rfalarm; /* PSC + 0x6e */
329 volatile u16 reserved22;
330 volatile u16 rfrptr; /* PSC + 0x72 */
331 volatile u16 reserved23;
332 volatile u16 rfwptr; /* PSC + 0x76 */
333 volatile u16 reserved24;
334 volatile u16 rflrfptr; /* PSC + 0x7a */
335 volatile u16 reserved25;
336 volatile u16 rflwfptr; /* PSC + 0x7e */
337 volatile u32 tfdata; /* PSC + 0x80 */
338 volatile u16 tfstat; /* PSC + 0x84 */
339 volatile u16 reserved26;
340 volatile u8 tfcntl; /* PSC + 0x88 */
341 volatile u8 reserved27[5];
342 volatile u16 tfalarm; /* PSC + 0x8e */
343 volatile u16 reserved28;
344 volatile u16 tfrptr; /* PSC + 0x92 */
345 volatile u16 reserved29;
346 volatile u16 tfwptr; /* PSC + 0x96 */
347 volatile u16 reserved30;
348 volatile u16 tflrfptr; /* PSC + 0x9a */
349 volatile u16 reserved31;
350 volatile u16 tflwfptr; /* PSC + 0x9e */
351};
352
353struct mpc5xxx_intr {
354 volatile u32 per_mask; /* INTR + 0x00 */
355 volatile u32 per_pri1; /* INTR + 0x04 */
356 volatile u32 per_pri2; /* INTR + 0x08 */
357 volatile u32 per_pri3; /* INTR + 0x0c */
358 volatile u32 ctrl; /* INTR + 0x10 */
359 volatile u32 main_mask; /* INTR + 0x14 */
360 volatile u32 main_pri1; /* INTR + 0x18 */
361 volatile u32 main_pri2; /* INTR + 0x1c */
362 volatile u32 reserved1; /* INTR + 0x20 */
363 volatile u32 enc_status; /* INTR + 0x24 */
364 volatile u32 crit_status; /* INTR + 0x28 */
365 volatile u32 main_status; /* INTR + 0x2c */
366 volatile u32 per_status; /* INTR + 0x30 */
367 volatile u32 reserved2; /* INTR + 0x34 */
368 volatile u32 per_error; /* INTR + 0x38 */
369};
370
371struct mpc5xxx_gpio {
372 volatile u32 port_config; /* GPIO + 0x00 */
373 volatile u32 simple_gpioe; /* GPIO + 0x04 */
374 volatile u32 simple_ode; /* GPIO + 0x08 */
375 volatile u32 simple_ddr; /* GPIO + 0x0c */
376 volatile u32 simple_dvo; /* GPIO + 0x10 */
377 volatile u32 simple_ival; /* GPIO + 0x14 */
378 volatile u8 outo_gpioe; /* GPIO + 0x18 */
379 volatile u8 reserved1[3]; /* GPIO + 0x19 */
380 volatile u8 outo_dvo; /* GPIO + 0x1c */
381 volatile u8 reserved2[3]; /* GPIO + 0x1d */
382 volatile u8 sint_gpioe; /* GPIO + 0x20 */
383 volatile u8 reserved3[3]; /* GPIO + 0x21 */
384 volatile u8 sint_ode; /* GPIO + 0x24 */
385 volatile u8 reserved4[3]; /* GPIO + 0x25 */
386 volatile u8 sint_ddr; /* GPIO + 0x28 */
387 volatile u8 reserved5[3]; /* GPIO + 0x29 */
388 volatile u8 sint_dvo; /* GPIO + 0x2c */
389 volatile u8 reserved6[3]; /* GPIO + 0x2d */
390 volatile u8 sint_inten; /* GPIO + 0x30 */
391 volatile u8 reserved7[3]; /* GPIO + 0x31 */
392 volatile u16 sint_itype; /* GPIO + 0x34 */
393 volatile u16 reserved8; /* GPIO + 0x36 */
394 volatile u8 gpio_control; /* GPIO + 0x38 */
395 volatile u8 reserved9[3]; /* GPIO + 0x39 */
396 volatile u8 sint_istat; /* GPIO + 0x3c */
397 volatile u8 sint_ival; /* GPIO + 0x3d */
398 volatile u8 bus_errs; /* GPIO + 0x3e */
399 volatile u8 reserved10; /* GPIO + 0x3f */
400};
401
402struct mpc5xxx_sdma {
403 volatile u32 taskBar; /* SDMA + 0x00 */
404 volatile u32 currentPointer; /* SDMA + 0x04 */
405 volatile u32 endPointer; /* SDMA + 0x08 */
406 volatile u32 variablePointer; /* SDMA + 0x0c */
407
408 volatile u8 IntVect1; /* SDMA + 0x10 */
409 volatile u8 IntVect2; /* SDMA + 0x11 */
410 volatile u16 PtdCntrl; /* SDMA + 0x12 */
411
412 volatile u32 IntPend; /* SDMA + 0x14 */
413 volatile u32 IntMask; /* SDMA + 0x18 */
414
415 volatile u16 tcr_0; /* SDMA + 0x1c */
416 volatile u16 tcr_1; /* SDMA + 0x1e */
417 volatile u16 tcr_2; /* SDMA + 0x20 */
418 volatile u16 tcr_3; /* SDMA + 0x22 */
419 volatile u16 tcr_4; /* SDMA + 0x24 */
420 volatile u16 tcr_5; /* SDMA + 0x26 */
421 volatile u16 tcr_6; /* SDMA + 0x28 */
422 volatile u16 tcr_7; /* SDMA + 0x2a */
423 volatile u16 tcr_8; /* SDMA + 0x2c */
424 volatile u16 tcr_9; /* SDMA + 0x2e */
425 volatile u16 tcr_a; /* SDMA + 0x30 */
426 volatile u16 tcr_b; /* SDMA + 0x32 */
427 volatile u16 tcr_c; /* SDMA + 0x34 */
428 volatile u16 tcr_d; /* SDMA + 0x36 */
429 volatile u16 tcr_e; /* SDMA + 0x38 */
430 volatile u16 tcr_f; /* SDMA + 0x3a */
431
432 volatile u8 IPR0; /* SDMA + 0x3c */
433 volatile u8 IPR1; /* SDMA + 0x3d */
434 volatile u8 IPR2; /* SDMA + 0x3e */
435 volatile u8 IPR3; /* SDMA + 0x3f */
436 volatile u8 IPR4; /* SDMA + 0x40 */
437 volatile u8 IPR5; /* SDMA + 0x41 */
438 volatile u8 IPR6; /* SDMA + 0x42 */
439 volatile u8 IPR7; /* SDMA + 0x43 */
440 volatile u8 IPR8; /* SDMA + 0x44 */
441 volatile u8 IPR9; /* SDMA + 0x45 */
442 volatile u8 IPR10; /* SDMA + 0x46 */
443 volatile u8 IPR11; /* SDMA + 0x47 */
444 volatile u8 IPR12; /* SDMA + 0x48 */
445 volatile u8 IPR13; /* SDMA + 0x49 */
446 volatile u8 IPR14; /* SDMA + 0x4a */
447 volatile u8 IPR15; /* SDMA + 0x4b */
448 volatile u8 IPR16; /* SDMA + 0x4c */
449 volatile u8 IPR17; /* SDMA + 0x4d */
450 volatile u8 IPR18; /* SDMA + 0x4e */
451 volatile u8 IPR19; /* SDMA + 0x4f */
452 volatile u8 IPR20; /* SDMA + 0x50 */
453 volatile u8 IPR21; /* SDMA + 0x51 */
454 volatile u8 IPR22; /* SDMA + 0x52 */
455 volatile u8 IPR23; /* SDMA + 0x53 */
456 volatile u8 IPR24; /* SDMA + 0x54 */
457 volatile u8 IPR25; /* SDMA + 0x55 */
458 volatile u8 IPR26; /* SDMA + 0x56 */
459 volatile u8 IPR27; /* SDMA + 0x57 */
460 volatile u8 IPR28; /* SDMA + 0x58 */
461 volatile u8 IPR29; /* SDMA + 0x59 */
462 volatile u8 IPR30; /* SDMA + 0x5a */
463 volatile u8 IPR31; /* SDMA + 0x5b */
464
465 volatile u32 res1; /* SDMA + 0x5c */
466 volatile u32 res2; /* SDMA + 0x60 */
467 volatile u32 res3; /* SDMA + 0x64 */
468 volatile u32 MDEDebug; /* SDMA + 0x68 */
469 volatile u32 ADSDebug; /* SDMA + 0x6c */
470 volatile u32 Value1; /* SDMA + 0x70 */
471 volatile u32 Value2; /* SDMA + 0x74 */
472 volatile u32 Control; /* SDMA + 0x78 */
473 volatile u32 Status; /* SDMA + 0x7c */
474 volatile u32 EU00; /* SDMA + 0x80 */
475 volatile u32 EU01; /* SDMA + 0x84 */
476 volatile u32 EU02; /* SDMA + 0x88 */
477 volatile u32 EU03; /* SDMA + 0x8c */
478 volatile u32 EU04; /* SDMA + 0x90 */
479 volatile u32 EU05; /* SDMA + 0x94 */
480 volatile u32 EU06; /* SDMA + 0x98 */
481 volatile u32 EU07; /* SDMA + 0x9c */
482 volatile u32 EU10; /* SDMA + 0xa0 */
483 volatile u32 EU11; /* SDMA + 0xa4 */
484 volatile u32 EU12; /* SDMA + 0xa8 */
485 volatile u32 EU13; /* SDMA + 0xac */
486 volatile u32 EU14; /* SDMA + 0xb0 */
487 volatile u32 EU15; /* SDMA + 0xb4 */
488 volatile u32 EU16; /* SDMA + 0xb8 */
489 volatile u32 EU17; /* SDMA + 0xbc */
490 volatile u32 EU20; /* SDMA + 0xc0 */
491 volatile u32 EU21; /* SDMA + 0xc4 */
492 volatile u32 EU22; /* SDMA + 0xc8 */
493 volatile u32 EU23; /* SDMA + 0xcc */
494 volatile u32 EU24; /* SDMA + 0xd0 */
495 volatile u32 EU25; /* SDMA + 0xd4 */
496 volatile u32 EU26; /* SDMA + 0xd8 */
497 volatile u32 EU27; /* SDMA + 0xdc */
498 volatile u32 EU30; /* SDMA + 0xe0 */
499 volatile u32 EU31; /* SDMA + 0xe4 */
500 volatile u32 EU32; /* SDMA + 0xe8 */
501 volatile u32 EU33; /* SDMA + 0xec */
502 volatile u32 EU34; /* SDMA + 0xf0 */
503 volatile u32 EU35; /* SDMA + 0xf4 */
504 volatile u32 EU36; /* SDMA + 0xf8 */
505 volatile u32 EU37; /* SDMA + 0xfc */
506};
507
508/* function prototypes */
509void loadtask(int basetask, int tasks);
510
511#endif /* __ASSEMBLY__ */
512
513#endif /* __ASMPPC_MPC5XXX_H */