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git01.mediatek.com / filogic / uboot / e42015b3e9ee7916e9003c70ca1eda62c1f0fb40 / . / arch / arm / dts / rk3588s.dtsi
blob: 5544f66c6ff411af3a3ccc9071682ace80410977 [file] [log] [blame]
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rk3588-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/power/rk3588-power.h>
10#include <dt-bindings/reset/rockchip,rk3588-cru.h>
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]11#include <dt-bindings/phy/phy.h>
12#include <dt-bindings/ata/ahci.h>
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]13
14/ {
15 compatible = "rockchip,rk3588";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu-map {
26 cluster0 {
27 core0 {
28 cpu = <&cpu_l0>;
29 };
30 core1 {
31 cpu = <&cpu_l1>;
32 };
33 core2 {
34 cpu = <&cpu_l2>;
35 };
36 core3 {
37 cpu = <&cpu_l3>;
38 };
39 };
40 cluster1 {
41 core0 {
42 cpu = <&cpu_b0>;
43 };
44 core1 {
45 cpu = <&cpu_b1>;
46 };
47 };
48 cluster2 {
49 core0 {
50 cpu = <&cpu_b2>;
51 };
52 core1 {
53 cpu = <&cpu_b3>;
54 };
55 };
56 };
57
58 cpu_l0: cpu@0 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a55";
61 reg = <0x0>;
62 enable-method = "psci";
63 capacity-dmips-mhz = <530>;
64 clocks = <&scmi_clk SCMI_CLK_CPUL>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]65 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
66 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]67 cpu-idle-states = <&CPU_SLEEP>;
68 i-cache-size = <32768>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <128>;
71 d-cache-size = <32768>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&l2_cache_l0>;
75 dynamic-power-coefficient = <228>;
76 #cooling-cells = <2>;
77 };
78
79 cpu_l1: cpu@100 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a55";
82 reg = <0x100>;
83 enable-method = "psci";
84 capacity-dmips-mhz = <530>;
85 clocks = <&scmi_clk SCMI_CLK_CPUL>;
86 cpu-idle-states = <&CPU_SLEEP>;
87 i-cache-size = <32768>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <128>;
90 d-cache-size = <32768>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&l2_cache_l1>;
94 dynamic-power-coefficient = <228>;
95 #cooling-cells = <2>;
96 };
97
98 cpu_l2: cpu@200 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a55";
101 reg = <0x200>;
102 enable-method = "psci";
103 capacity-dmips-mhz = <530>;
104 clocks = <&scmi_clk SCMI_CLK_CPUL>;
105 cpu-idle-states = <&CPU_SLEEP>;
106 i-cache-size = <32768>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <128>;
109 d-cache-size = <32768>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&l2_cache_l2>;
113 dynamic-power-coefficient = <228>;
114 #cooling-cells = <2>;
115 };
116
117 cpu_l3: cpu@300 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a55";
120 reg = <0x300>;
121 enable-method = "psci";
122 capacity-dmips-mhz = <530>;
123 clocks = <&scmi_clk SCMI_CLK_CPUL>;
124 cpu-idle-states = <&CPU_SLEEP>;
125 i-cache-size = <32768>;
126 i-cache-line-size = <64>;
127 i-cache-sets = <128>;
128 d-cache-size = <32768>;
129 d-cache-line-size = <64>;
130 d-cache-sets = <128>;
131 next-level-cache = <&l2_cache_l3>;
132 dynamic-power-coefficient = <228>;
133 #cooling-cells = <2>;
134 };
135
136 cpu_b0: cpu@400 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a76";
139 reg = <0x400>;
140 enable-method = "psci";
141 capacity-dmips-mhz = <1024>;
142 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]143 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
144 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]145 cpu-idle-states = <&CPU_SLEEP>;
146 i-cache-size = <65536>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <65536>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <256>;
152 next-level-cache = <&l2_cache_b0>;
153 dynamic-power-coefficient = <416>;
154 #cooling-cells = <2>;
155 };
156
157 cpu_b1: cpu@500 {
158 device_type = "cpu";
159 compatible = "arm,cortex-a76";
160 reg = <0x500>;
161 enable-method = "psci";
162 capacity-dmips-mhz = <1024>;
163 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
164 cpu-idle-states = <&CPU_SLEEP>;
165 i-cache-size = <65536>;
166 i-cache-line-size = <64>;
167 i-cache-sets = <256>;
168 d-cache-size = <65536>;
169 d-cache-line-size = <64>;
170 d-cache-sets = <256>;
171 next-level-cache = <&l2_cache_b1>;
172 dynamic-power-coefficient = <416>;
173 #cooling-cells = <2>;
174 };
175
176 cpu_b2: cpu@600 {
177 device_type = "cpu";
178 compatible = "arm,cortex-a76";
179 reg = <0x600>;
180 enable-method = "psci";
181 capacity-dmips-mhz = <1024>;
182 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]183 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
184 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]185 cpu-idle-states = <&CPU_SLEEP>;
186 i-cache-size = <65536>;
187 i-cache-line-size = <64>;
188 i-cache-sets = <256>;
189 d-cache-size = <65536>;
190 d-cache-line-size = <64>;
191 d-cache-sets = <256>;
192 next-level-cache = <&l2_cache_b2>;
193 dynamic-power-coefficient = <416>;
194 #cooling-cells = <2>;
195 };
196
197 cpu_b3: cpu@700 {
198 device_type = "cpu";
199 compatible = "arm,cortex-a76";
200 reg = <0x700>;
201 enable-method = "psci";
202 capacity-dmips-mhz = <1024>;
203 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
204 cpu-idle-states = <&CPU_SLEEP>;
205 i-cache-size = <65536>;
206 i-cache-line-size = <64>;
207 i-cache-sets = <256>;
208 d-cache-size = <65536>;
209 d-cache-line-size = <64>;
210 d-cache-sets = <256>;
211 next-level-cache = <&l2_cache_b3>;
212 dynamic-power-coefficient = <416>;
213 #cooling-cells = <2>;
214 };
215
216 idle-states {
217 entry-method = "psci";
218 CPU_SLEEP: cpu-sleep {
219 compatible = "arm,idle-state";
220 local-timer-stop;
221 arm,psci-suspend-param = <0x0010000>;
222 entry-latency-us = <100>;
223 exit-latency-us = <120>;
224 min-residency-us = <1000>;
225 };
226 };
227
228 l2_cache_l0: l2-cache-l0 {
229 compatible = "cache";
230 cache-size = <131072>;
231 cache-line-size = <64>;
232 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]233 cache-level = <2>;
234 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]235 next-level-cache = <&l3_cache>;
236 };
237
238 l2_cache_l1: l2-cache-l1 {
239 compatible = "cache";
240 cache-size = <131072>;
241 cache-line-size = <64>;
242 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]243 cache-level = <2>;
244 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]245 next-level-cache = <&l3_cache>;
246 };
247
248 l2_cache_l2: l2-cache-l2 {
249 compatible = "cache";
250 cache-size = <131072>;
251 cache-line-size = <64>;
252 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]253 cache-level = <2>;
254 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]255 next-level-cache = <&l3_cache>;
256 };
257
258 l2_cache_l3: l2-cache-l3 {
259 compatible = "cache";
260 cache-size = <131072>;
261 cache-line-size = <64>;
262 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]263 cache-level = <2>;
264 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]265 next-level-cache = <&l3_cache>;
266 };
267
268 l2_cache_b0: l2-cache-b0 {
269 compatible = "cache";
270 cache-size = <524288>;
271 cache-line-size = <64>;
272 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]273 cache-level = <2>;
274 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]275 next-level-cache = <&l3_cache>;
276 };
277
278 l2_cache_b1: l2-cache-b1 {
279 compatible = "cache";
280 cache-size = <524288>;
281 cache-line-size = <64>;
282 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]283 cache-level = <2>;
284 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]285 next-level-cache = <&l3_cache>;
286 };
287
288 l2_cache_b2: l2-cache-b2 {
289 compatible = "cache";
290 cache-size = <524288>;
291 cache-line-size = <64>;
292 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]293 cache-level = <2>;
294 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]295 next-level-cache = <&l3_cache>;
296 };
297
298 l2_cache_b3: l2-cache-b3 {
299 compatible = "cache";
300 cache-size = <524288>;
301 cache-line-size = <64>;
302 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]303 cache-level = <2>;
304 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]305 next-level-cache = <&l3_cache>;
306 };
307
308 l3_cache: l3-cache {
309 compatible = "cache";
310 cache-size = <3145728>;
311 cache-line-size = <64>;
312 cache-sets = <4096>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]313 cache-level = <3>;
314 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]315 };
316 };
317
318 firmware {
319 optee: optee {
320 compatible = "linaro,optee-tz";
321 method = "smc";
322 };
323
324 scmi: scmi {
325 compatible = "arm,scmi-smc";
326 arm,smc-id = <0x82000010>;
327 shmem = <&scmi_shmem>;
328 #address-cells = <1>;
329 #size-cells = <0>;
330
331 scmi_clk: protocol@14 {
332 reg = <0x14>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]333 #clock-cells = <1>;
334 };
335
336 scmi_reset: protocol@16 {
337 reg = <0x16>;
338 #reset-cells = <1>;
339 };
340 };
341 };
342
343 pmu-a55 {
344 compatible = "arm,cortex-a55-pmu";
345 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
346 };
347
348 pmu-a76 {
349 compatible = "arm,cortex-a76-pmu";
350 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
351 };
352
353 psci {
354 compatible = "arm,psci-1.0";
355 method = "smc";
356 };
357
358 spll: clock-0 {
359 compatible = "fixed-clock";
360 clock-frequency = <702000000>;
361 clock-output-names = "spll";
362 #clock-cells = <0>;
363 };
364
365 timer {
366 compatible = "arm,armv8-timer";
367 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
368 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
369 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
370 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
371 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
372 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
373 };
374
375 xin24m: clock-1 {
376 compatible = "fixed-clock";
377 clock-frequency = <24000000>;
378 clock-output-names = "xin24m";
379 #clock-cells = <0>;
380 };
381
382 xin32k: clock-2 {
383 compatible = "fixed-clock";
384 clock-frequency = <32768>;
385 clock-output-names = "xin32k";
386 #clock-cells = <0>;
387 };
388
389 pmu_sram: sram@10f000 {
390 compatible = "mmio-sram";
391 reg = <0x0 0x0010f000 0x0 0x100>;
392 ranges = <0 0x0 0x0010f000 0x100>;
393 #address-cells = <1>;
394 #size-cells = <1>;
395
396 scmi_shmem: sram@0 {
397 compatible = "arm,scmi-shmem";
398 reg = <0x0 0x100>;
399 };
400 };
401
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]402 usb_host0_ehci: usb@fc800000 {
403 compatible = "rockchip,rk3588-ehci", "generic-ehci";
404 reg = <0x0 0xfc800000 0x0 0x40000>;
405 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
407 phys = <&u2phy2_host>;
408 phy-names = "usb";
409 power-domains = <&power RK3588_PD_USB>;
410 status = "disabled";
411 };
412
413 usb_host0_ohci: usb@fc840000 {
414 compatible = "rockchip,rk3588-ohci", "generic-ohci";
415 reg = <0x0 0xfc840000 0x0 0x40000>;
416 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
418 phys = <&u2phy2_host>;
419 phy-names = "usb";
420 power-domains = <&power RK3588_PD_USB>;
421 status = "disabled";
422 };
423
424 usb_host1_ehci: usb@fc880000 {
425 compatible = "rockchip,rk3588-ehci", "generic-ehci";
426 reg = <0x0 0xfc880000 0x0 0x40000>;
427 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
429 phys = <&u2phy3_host>;
430 phy-names = "usb";
431 power-domains = <&power RK3588_PD_USB>;
432 status = "disabled";
433 };
434
435 usb_host1_ohci: usb@fc8c0000 {
436 compatible = "rockchip,rk3588-ohci", "generic-ohci";
437 reg = <0x0 0xfc8c0000 0x0 0x40000>;
438 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
440 phys = <&u2phy3_host>;
441 phy-names = "usb";
442 power-domains = <&power RK3588_PD_USB>;
443 status = "disabled";
444 };
445
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]446 sys_grf: syscon@fd58c000 {
447 compatible = "rockchip,rk3588-sys-grf", "syscon";
448 reg = <0x0 0xfd58c000 0x0 0x1000>;
449 };
450
451 php_grf: syscon@fd5b0000 {
452 compatible = "rockchip,rk3588-php-grf", "syscon";
453 reg = <0x0 0xfd5b0000 0x0 0x1000>;
454 };
455
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]456 pipe_phy0_grf: syscon@fd5bc000 {
457 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
458 reg = <0x0 0xfd5bc000 0x0 0x100>;
459 };
460
461 pipe_phy2_grf: syscon@fd5c4000 {
462 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
463 reg = <0x0 0xfd5c4000 0x0 0x100>;
464 };
465
466 usb2phy2_grf: syscon@fd5d8000 {
467 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
468 reg = <0x0 0xfd5d8000 0x0 0x4000>;
469 #address-cells = <1>;
470 #size-cells = <1>;
471
472 u2phy2: usb2-phy@8000 {
473 compatible = "rockchip,rk3588-usb2phy";
474 reg = <0x8000 0x10>;
475 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
476 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
477 reset-names = "phy", "apb";
478 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
479 clock-names = "phyclk";
480 clock-output-names = "usb480m_phy2";
481 #clock-cells = <0>;
482 status = "disabled";
483
484 u2phy2_host: host-port {
485 #phy-cells = <0>;
486 status = "disabled";
487 };
488 };
489 };
490
491 usb2phy3_grf: syscon@fd5dc000 {
492 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
493 reg = <0x0 0xfd5dc000 0x0 0x4000>;
494 #address-cells = <1>;
495 #size-cells = <1>;
496
497 u2phy3: usb2-phy@c000 {
498 compatible = "rockchip,rk3588-usb2phy";
499 reg = <0xc000 0x10>;
500 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
501 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
502 reset-names = "phy", "apb";
503 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
504 clock-names = "phyclk";
505 clock-output-names = "usb480m_phy3";
506 #clock-cells = <0>;
507 status = "disabled";
508
509 u2phy3_host: host-port {
510 #phy-cells = <0>;
511 status = "disabled";
512 };
513 };
514 };
515
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]516 ioc: syscon@fd5f0000 {
517 compatible = "rockchip,rk3588-ioc", "syscon";
518 reg = <0x0 0xfd5f0000 0x0 0x10000>;
519 };
520
521 system_sram1: sram@fd600000 {
522 compatible = "mmio-sram";
523 reg = <0x0 0xfd600000 0x0 0x100000>;
524 ranges = <0x0 0x0 0xfd600000 0x100000>;
525 #address-cells = <1>;
526 #size-cells = <1>;
527 };
528
529 cru: clock-controller@fd7c0000 {
530 compatible = "rockchip,rk3588-cru";
531 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
532 assigned-clocks =
533 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
534 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
535 <&cru ACLK_CENTER_ROOT>,
536 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
537 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
538 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
539 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
540 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
541 <&cru CLK_GPU>;
542 assigned-clock-rates =
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]543 <1100000000>, <786432000>,
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]544 <850000000>, <1188000000>,
545 <702000000>,
546 <400000000>, <500000000>,
547 <800000000>, <100000000>,
548 <400000000>, <100000000>,
549 <200000000>, <500000000>,
550 <375000000>, <150000000>,
551 <200000000>;
552 rockchip,grf = <&php_grf>;
553 #clock-cells = <1>;
554 #reset-cells = <1>;
555 };
556
557 i2c0: i2c@fd880000 {
558 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
559 reg = <0x0 0xfd880000 0x0 0x1000>;
560 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
561 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
562 clock-names = "i2c", "pclk";
563 pinctrl-0 = <&i2c0m0_xfer>;
564 pinctrl-names = "default";
565 #address-cells = <1>;
566 #size-cells = <0>;
567 status = "disabled";
568 };
569
570 uart0: serial@fd890000 {
571 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
572 reg = <0x0 0xfd890000 0x0 0x100>;
573 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
574 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
575 clock-names = "baudclk", "apb_pclk";
576 dmas = <&dmac0 6>, <&dmac0 7>;
577 dma-names = "tx", "rx";
578 pinctrl-0 = <&uart0m1_xfer>;
579 pinctrl-names = "default";
580 reg-shift = <2>;
581 reg-io-width = <4>;
582 status = "disabled";
583 };
584
585 pwm0: pwm@fd8b0000 {
586 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
587 reg = <0x0 0xfd8b0000 0x0 0x10>;
588 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
589 clock-names = "pwm", "pclk";
590 pinctrl-0 = <&pwm0m0_pins>;
591 pinctrl-names = "default";
592 #pwm-cells = <3>;
593 status = "disabled";
594 };
595
596 pwm1: pwm@fd8b0010 {
597 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
598 reg = <0x0 0xfd8b0010 0x0 0x10>;
599 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
600 clock-names = "pwm", "pclk";
601 pinctrl-0 = <&pwm1m0_pins>;
602 pinctrl-names = "default";
603 #pwm-cells = <3>;
604 status = "disabled";
605 };
606
607 pwm2: pwm@fd8b0020 {
608 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
609 reg = <0x0 0xfd8b0020 0x0 0x10>;
610 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
611 clock-names = "pwm", "pclk";
612 pinctrl-0 = <&pwm2m0_pins>;
613 pinctrl-names = "default";
614 #pwm-cells = <3>;
615 status = "disabled";
616 };
617
618 pwm3: pwm@fd8b0030 {
619 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
620 reg = <0x0 0xfd8b0030 0x0 0x10>;
621 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
622 clock-names = "pwm", "pclk";
623 pinctrl-0 = <&pwm3m0_pins>;
624 pinctrl-names = "default";
625 #pwm-cells = <3>;
626 status = "disabled";
627 };
628
629 pmu: power-management@fd8d8000 {
630 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
631 reg = <0x0 0xfd8d8000 0x0 0x400>;
632
633 power: power-controller {
634 compatible = "rockchip,rk3588-power-controller";
635 #address-cells = <1>;
636 #power-domain-cells = <1>;
637 #size-cells = <0>;
638 status = "okay";
639
640 /* These power domains are grouped by VD_NPU */
641 power-domain@RK3588_PD_NPU {
642 reg = <RK3588_PD_NPU>;
643 #power-domain-cells = <0>;
644 #address-cells = <1>;
645 #size-cells = <0>;
646
647 power-domain@RK3588_PD_NPUTOP {
648 reg = <RK3588_PD_NPUTOP>;
649 clocks = <&cru HCLK_NPU_ROOT>,
650 <&cru PCLK_NPU_ROOT>,
651 <&cru CLK_NPU_DSU0>,
652 <&cru HCLK_NPU_CM0_ROOT>;
653 pm_qos = <&qos_npu0_mwr>,
654 <&qos_npu0_mro>,
655 <&qos_mcu_npu>;
656 #power-domain-cells = <0>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659
660 power-domain@RK3588_PD_NPU1 {
661 reg = <RK3588_PD_NPU1>;
662 clocks = <&cru HCLK_NPU_ROOT>,
663 <&cru PCLK_NPU_ROOT>,
664 <&cru CLK_NPU_DSU0>;
665 pm_qos = <&qos_npu1>;
666 #power-domain-cells = <0>;
667 };
668 power-domain@RK3588_PD_NPU2 {
669 reg = <RK3588_PD_NPU2>;
670 clocks = <&cru HCLK_NPU_ROOT>,
671 <&cru PCLK_NPU_ROOT>,
672 <&cru CLK_NPU_DSU0>;
673 pm_qos = <&qos_npu2>;
674 #power-domain-cells = <0>;
675 };
676 };
677 };
678 /* These power domains are grouped by VD_GPU */
679 power-domain@RK3588_PD_GPU {
680 reg = <RK3588_PD_GPU>;
681 clocks = <&cru CLK_GPU>,
682 <&cru CLK_GPU_COREGROUP>,
683 <&cru CLK_GPU_STACKS>;
684 pm_qos = <&qos_gpu_m0>,
685 <&qos_gpu_m1>,
686 <&qos_gpu_m2>,
687 <&qos_gpu_m3>;
688 #power-domain-cells = <0>;
689 };
690 /* These power domains are grouped by VD_VCODEC */
691 power-domain@RK3588_PD_VCODEC {
692 reg = <RK3588_PD_VCODEC>;
693 #address-cells = <1>;
694 #size-cells = <0>;
695 #power-domain-cells = <0>;
696
697 power-domain@RK3588_PD_RKVDEC0 {
698 reg = <RK3588_PD_RKVDEC0>;
699 clocks = <&cru HCLK_RKVDEC0>,
700 <&cru HCLK_VDPU_ROOT>,
701 <&cru ACLK_VDPU_ROOT>,
702 <&cru ACLK_RKVDEC0>,
703 <&cru ACLK_RKVDEC_CCU>;
704 pm_qos = <&qos_rkvdec0>;
705 #power-domain-cells = <0>;
706 };
707 power-domain@RK3588_PD_RKVDEC1 {
708 reg = <RK3588_PD_RKVDEC1>;
709 clocks = <&cru HCLK_RKVDEC1>,
710 <&cru HCLK_VDPU_ROOT>,
711 <&cru ACLK_VDPU_ROOT>,
712 <&cru ACLK_RKVDEC1>;
713 pm_qos = <&qos_rkvdec1>;
714 #power-domain-cells = <0>;
715 };
716 power-domain@RK3588_PD_VENC0 {
717 reg = <RK3588_PD_VENC0>;
718 clocks = <&cru HCLK_RKVENC0>,
719 <&cru ACLK_RKVENC0>;
720 pm_qos = <&qos_rkvenc0_m0ro>,
721 <&qos_rkvenc0_m1ro>,
722 <&qos_rkvenc0_m2wo>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 #power-domain-cells = <0>;
726
727 power-domain@RK3588_PD_VENC1 {
728 reg = <RK3588_PD_VENC1>;
729 clocks = <&cru HCLK_RKVENC1>,
730 <&cru HCLK_RKVENC0>,
731 <&cru ACLK_RKVENC0>,
732 <&cru ACLK_RKVENC1>;
733 pm_qos = <&qos_rkvenc1_m0ro>,
734 <&qos_rkvenc1_m1ro>,
735 <&qos_rkvenc1_m2wo>;
736 #power-domain-cells = <0>;
737 };
738 };
739 };
740 /* These power domains are grouped by VD_LOGIC */
741 power-domain@RK3588_PD_VDPU {
742 reg = <RK3588_PD_VDPU>;
743 clocks = <&cru HCLK_VDPU_ROOT>,
744 <&cru ACLK_VDPU_LOW_ROOT>,
745 <&cru ACLK_VDPU_ROOT>,
746 <&cru ACLK_JPEG_DECODER_ROOT>,
747 <&cru ACLK_IEP2P0>,
748 <&cru HCLK_IEP2P0>,
749 <&cru ACLK_JPEG_ENCODER0>,
750 <&cru HCLK_JPEG_ENCODER0>,
751 <&cru ACLK_JPEG_ENCODER1>,
752 <&cru HCLK_JPEG_ENCODER1>,
753 <&cru ACLK_JPEG_ENCODER2>,
754 <&cru HCLK_JPEG_ENCODER2>,
755 <&cru ACLK_JPEG_ENCODER3>,
756 <&cru HCLK_JPEG_ENCODER3>,
757 <&cru ACLK_JPEG_DECODER>,
758 <&cru HCLK_JPEG_DECODER>,
759 <&cru ACLK_RGA2>,
760 <&cru HCLK_RGA2>;
761 pm_qos = <&qos_iep>,
762 <&qos_jpeg_dec>,
763 <&qos_jpeg_enc0>,
764 <&qos_jpeg_enc1>,
765 <&qos_jpeg_enc2>,
766 <&qos_jpeg_enc3>,
767 <&qos_rga2_mro>,
768 <&qos_rga2_mwo>;
769 #address-cells = <1>;
770 #size-cells = <0>;
771 #power-domain-cells = <0>;
772
773
774 power-domain@RK3588_PD_AV1 {
775 reg = <RK3588_PD_AV1>;
776 clocks = <&cru PCLK_AV1>,
777 <&cru ACLK_AV1>,
778 <&cru HCLK_VDPU_ROOT>;
779 pm_qos = <&qos_av1>;
780 #power-domain-cells = <0>;
781 };
782 power-domain@RK3588_PD_RKVDEC0 {
783 reg = <RK3588_PD_RKVDEC0>;
784 clocks = <&cru HCLK_RKVDEC0>,
785 <&cru HCLK_VDPU_ROOT>,
786 <&cru ACLK_VDPU_ROOT>,
787 <&cru ACLK_RKVDEC0>;
788 pm_qos = <&qos_rkvdec0>;
789 #power-domain-cells = <0>;
790 };
791 power-domain@RK3588_PD_RKVDEC1 {
792 reg = <RK3588_PD_RKVDEC1>;
793 clocks = <&cru HCLK_RKVDEC1>,
794 <&cru HCLK_VDPU_ROOT>,
795 <&cru ACLK_VDPU_ROOT>;
796 pm_qos = <&qos_rkvdec1>;
797 #power-domain-cells = <0>;
798 };
799 power-domain@RK3588_PD_RGA30 {
800 reg = <RK3588_PD_RGA30>;
801 clocks = <&cru ACLK_RGA3_0>,
802 <&cru HCLK_RGA3_0>;
803 pm_qos = <&qos_rga3_0>;
804 #power-domain-cells = <0>;
805 };
806 };
807 power-domain@RK3588_PD_VOP {
808 reg = <RK3588_PD_VOP>;
809 clocks = <&cru PCLK_VOP_ROOT>,
810 <&cru HCLK_VOP_ROOT>,
811 <&cru ACLK_VOP>;
812 pm_qos = <&qos_vop_m0>,
813 <&qos_vop_m1>;
814 #address-cells = <1>;
815 #size-cells = <0>;
816 #power-domain-cells = <0>;
817
818 power-domain@RK3588_PD_VO0 {
819 reg = <RK3588_PD_VO0>;
820 clocks = <&cru PCLK_VO0_ROOT>,
821 <&cru PCLK_VO0_S_ROOT>,
822 <&cru HCLK_VO0_S_ROOT>,
823 <&cru ACLK_VO0_ROOT>,
824 <&cru HCLK_HDCP0>,
825 <&cru ACLK_HDCP0>,
826 <&cru HCLK_VOP_ROOT>;
827 pm_qos = <&qos_hdcp0>;
828 #power-domain-cells = <0>;
829 };
830 };
831 power-domain@RK3588_PD_VO1 {
832 reg = <RK3588_PD_VO1>;
833 clocks = <&cru PCLK_VO1_ROOT>,
834 <&cru PCLK_VO1_S_ROOT>,
835 <&cru HCLK_VO1_S_ROOT>,
836 <&cru HCLK_HDCP1>,
837 <&cru ACLK_HDCP1>,
838 <&cru ACLK_HDMIRX_ROOT>,
839 <&cru HCLK_VO1USB_TOP_ROOT>;
840 pm_qos = <&qos_hdcp1>,
841 <&qos_hdmirx>;
842 #power-domain-cells = <0>;
843 };
844 power-domain@RK3588_PD_VI {
845 reg = <RK3588_PD_VI>;
846 clocks = <&cru HCLK_VI_ROOT>,
847 <&cru PCLK_VI_ROOT>,
848 <&cru HCLK_ISP0>,
849 <&cru ACLK_ISP0>,
850 <&cru HCLK_VICAP>,
851 <&cru ACLK_VICAP>;
852 pm_qos = <&qos_isp0_mro>,
853 <&qos_isp0_mwo>,
854 <&qos_vicap_m0>,
855 <&qos_vicap_m1>;
856 #address-cells = <1>;
857 #size-cells = <0>;
858 #power-domain-cells = <0>;
859
860 power-domain@RK3588_PD_ISP1 {
861 reg = <RK3588_PD_ISP1>;
862 clocks = <&cru HCLK_ISP1>,
863 <&cru ACLK_ISP1>,
864 <&cru HCLK_VI_ROOT>,
865 <&cru PCLK_VI_ROOT>;
866 pm_qos = <&qos_isp1_mwo>,
867 <&qos_isp1_mro>;
868 #power-domain-cells = <0>;
869 };
870 power-domain@RK3588_PD_FEC {
871 reg = <RK3588_PD_FEC>;
872 clocks = <&cru HCLK_FISHEYE0>,
873 <&cru ACLK_FISHEYE0>,
874 <&cru HCLK_FISHEYE1>,
875 <&cru ACLK_FISHEYE1>,
876 <&cru PCLK_VI_ROOT>;
877 pm_qos = <&qos_fisheye0>,
878 <&qos_fisheye1>;
879 #power-domain-cells = <0>;
880 };
881 };
882 power-domain@RK3588_PD_RGA31 {
883 reg = <RK3588_PD_RGA31>;
884 clocks = <&cru HCLK_RGA3_1>,
885 <&cru ACLK_RGA3_1>;
886 pm_qos = <&qos_rga3_1>;
887 #power-domain-cells = <0>;
888 };
889 power-domain@RK3588_PD_USB {
890 reg = <RK3588_PD_USB>;
891 clocks = <&cru PCLK_PHP_ROOT>,
892 <&cru ACLK_USB_ROOT>,
893 <&cru HCLK_USB_ROOT>,
894 <&cru HCLK_HOST0>,
895 <&cru HCLK_HOST_ARB0>,
896 <&cru HCLK_HOST1>,
897 <&cru HCLK_HOST_ARB1>;
898 pm_qos = <&qos_usb3_0>,
899 <&qos_usb3_1>,
900 <&qos_usb2host_0>,
901 <&qos_usb2host_1>;
902 #power-domain-cells = <0>;
903 };
904 power-domain@RK3588_PD_GMAC {
905 reg = <RK3588_PD_GMAC>;
906 clocks = <&cru PCLK_PHP_ROOT>,
907 <&cru ACLK_PCIE_ROOT>,
908 <&cru ACLK_PHP_ROOT>;
909 #power-domain-cells = <0>;
910 };
911 power-domain@RK3588_PD_PCIE {
912 reg = <RK3588_PD_PCIE>;
913 clocks = <&cru PCLK_PHP_ROOT>,
914 <&cru ACLK_PCIE_ROOT>,
915 <&cru ACLK_PHP_ROOT>;
916 #power-domain-cells = <0>;
917 };
918 power-domain@RK3588_PD_SDIO {
919 reg = <RK3588_PD_SDIO>;
920 clocks = <&cru HCLK_SDIO>,
921 <&cru HCLK_NVM_ROOT>;
922 pm_qos = <&qos_sdio>;
923 #power-domain-cells = <0>;
924 };
925 power-domain@RK3588_PD_AUDIO {
926 reg = <RK3588_PD_AUDIO>;
927 clocks = <&cru HCLK_AUDIO_ROOT>,
928 <&cru PCLK_AUDIO_ROOT>;
929 #power-domain-cells = <0>;
930 };
931 power-domain@RK3588_PD_SDMMC {
932 reg = <RK3588_PD_SDMMC>;
933 pm_qos = <&qos_sdmmc>;
934 #power-domain-cells = <0>;
935 };
936 };
937 };
938
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]939 i2s4_8ch: i2s@fddc0000 {
940 compatible = "rockchip,rk3588-i2s-tdm";
941 reg = <0x0 0xfddc0000 0x0 0x1000>;
942 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
943 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
944 clock-names = "mclk_tx", "mclk_rx", "hclk";
945 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
946 assigned-clock-parents = <&cru PLL_AUPLL>;
947 dmas = <&dmac2 0>;
948 dma-names = "tx";
949 power-domains = <&power RK3588_PD_VO0>;
950 resets = <&cru SRST_M_I2S4_8CH_TX>;
951 reset-names = "tx-m";
952 #sound-dai-cells = <0>;
953 status = "disabled";
954 };
955
956 i2s5_8ch: i2s@fddf0000 {
957 compatible = "rockchip,rk3588-i2s-tdm";
958 reg = <0x0 0xfddf0000 0x0 0x1000>;
959 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
960 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
961 clock-names = "mclk_tx", "mclk_rx", "hclk";
962 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
963 assigned-clock-parents = <&cru PLL_AUPLL>;
964 dmas = <&dmac2 2>;
965 dma-names = "tx";
966 power-domains = <&power RK3588_PD_VO1>;
967 resets = <&cru SRST_M_I2S5_8CH_TX>;
968 reset-names = "tx-m";
969 #sound-dai-cells = <0>;
970 status = "disabled";
971 };
972
973 i2s9_8ch: i2s@fddfc000 {
974 compatible = "rockchip,rk3588-i2s-tdm";
975 reg = <0x0 0xfddfc000 0x0 0x1000>;
976 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
977 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
978 clock-names = "mclk_tx", "mclk_rx", "hclk";
979 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
980 assigned-clock-parents = <&cru PLL_AUPLL>;
981 dmas = <&dmac2 23>;
982 dma-names = "rx";
983 power-domains = <&power RK3588_PD_VO1>;
984 resets = <&cru SRST_M_I2S9_8CH_RX>;
985 reset-names = "rx-m";
986 #sound-dai-cells = <0>;
987 status = "disabled";
988 };
989
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]990 qos_gpu_m0: qos@fdf35000 {
991 compatible = "rockchip,rk3588-qos", "syscon";
992 reg = <0x0 0xfdf35000 0x0 0x20>;
993 };
994
995 qos_gpu_m1: qos@fdf35200 {
996 compatible = "rockchip,rk3588-qos", "syscon";
997 reg = <0x0 0xfdf35200 0x0 0x20>;
998 };
999
1000 qos_gpu_m2: qos@fdf35400 {
1001 compatible = "rockchip,rk3588-qos", "syscon";
1002 reg = <0x0 0xfdf35400 0x0 0x20>;
1003 };
1004
1005 qos_gpu_m3: qos@fdf35600 {
1006 compatible = "rockchip,rk3588-qos", "syscon";
1007 reg = <0x0 0xfdf35600 0x0 0x20>;
1008 };
1009
1010 qos_rga3_1: qos@fdf36000 {
1011 compatible = "rockchip,rk3588-qos", "syscon";
1012 reg = <0x0 0xfdf36000 0x0 0x20>;
1013 };
1014
1015 qos_sdio: qos@fdf39000 {
1016 compatible = "rockchip,rk3588-qos", "syscon";
1017 reg = <0x0 0xfdf39000 0x0 0x20>;
1018 };
1019
1020 qos_sdmmc: qos@fdf3d800 {
1021 compatible = "rockchip,rk3588-qos", "syscon";
1022 reg = <0x0 0xfdf3d800 0x0 0x20>;
1023 };
1024
1025 qos_usb3_1: qos@fdf3e000 {
1026 compatible = "rockchip,rk3588-qos", "syscon";
1027 reg = <0x0 0xfdf3e000 0x0 0x20>;
1028 };
1029
1030 qos_usb3_0: qos@fdf3e200 {
1031 compatible = "rockchip,rk3588-qos", "syscon";
1032 reg = <0x0 0xfdf3e200 0x0 0x20>;
1033 };
1034
1035 qos_usb2host_0: qos@fdf3e400 {
1036 compatible = "rockchip,rk3588-qos", "syscon";
1037 reg = <0x0 0xfdf3e400 0x0 0x20>;
1038 };
1039
1040 qos_usb2host_1: qos@fdf3e600 {
1041 compatible = "rockchip,rk3588-qos", "syscon";
1042 reg = <0x0 0xfdf3e600 0x0 0x20>;
1043 };
1044
1045 qos_fisheye0: qos@fdf40000 {
1046 compatible = "rockchip,rk3588-qos", "syscon";
1047 reg = <0x0 0xfdf40000 0x0 0x20>;
1048 };
1049
1050 qos_fisheye1: qos@fdf40200 {
1051 compatible = "rockchip,rk3588-qos", "syscon";
1052 reg = <0x0 0xfdf40200 0x0 0x20>;
1053 };
1054
1055 qos_isp0_mro: qos@fdf40400 {
1056 compatible = "rockchip,rk3588-qos", "syscon";
1057 reg = <0x0 0xfdf40400 0x0 0x20>;
1058 };
1059
1060 qos_isp0_mwo: qos@fdf40500 {
1061 compatible = "rockchip,rk3588-qos", "syscon";
1062 reg = <0x0 0xfdf40500 0x0 0x20>;
1063 };
1064
1065 qos_vicap_m0: qos@fdf40600 {
1066 compatible = "rockchip,rk3588-qos", "syscon";
1067 reg = <0x0 0xfdf40600 0x0 0x20>;
1068 };
1069
1070 qos_vicap_m1: qos@fdf40800 {
1071 compatible = "rockchip,rk3588-qos", "syscon";
1072 reg = <0x0 0xfdf40800 0x0 0x20>;
1073 };
1074
1075 qos_isp1_mwo: qos@fdf41000 {
1076 compatible = "rockchip,rk3588-qos", "syscon";
1077 reg = <0x0 0xfdf41000 0x0 0x20>;
1078 };
1079
1080 qos_isp1_mro: qos@fdf41100 {
1081 compatible = "rockchip,rk3588-qos", "syscon";
1082 reg = <0x0 0xfdf41100 0x0 0x20>;
1083 };
1084
1085 qos_rkvenc0_m0ro: qos@fdf60000 {
1086 compatible = "rockchip,rk3588-qos", "syscon";
1087 reg = <0x0 0xfdf60000 0x0 0x20>;
1088 };
1089
1090 qos_rkvenc0_m1ro: qos@fdf60200 {
1091 compatible = "rockchip,rk3588-qos", "syscon";
1092 reg = <0x0 0xfdf60200 0x0 0x20>;
1093 };
1094
1095 qos_rkvenc0_m2wo: qos@fdf60400 {
1096 compatible = "rockchip,rk3588-qos", "syscon";
1097 reg = <0x0 0xfdf60400 0x0 0x20>;
1098 };
1099
1100 qos_rkvenc1_m0ro: qos@fdf61000 {
1101 compatible = "rockchip,rk3588-qos", "syscon";
1102 reg = <0x0 0xfdf61000 0x0 0x20>;
1103 };
1104
1105 qos_rkvenc1_m1ro: qos@fdf61200 {
1106 compatible = "rockchip,rk3588-qos", "syscon";
1107 reg = <0x0 0xfdf61200 0x0 0x20>;
1108 };
1109
1110 qos_rkvenc1_m2wo: qos@fdf61400 {
1111 compatible = "rockchip,rk3588-qos", "syscon";
1112 reg = <0x0 0xfdf61400 0x0 0x20>;
1113 };
1114
1115 qos_rkvdec0: qos@fdf62000 {
1116 compatible = "rockchip,rk3588-qos", "syscon";
1117 reg = <0x0 0xfdf62000 0x0 0x20>;
1118 };
1119
1120 qos_rkvdec1: qos@fdf63000 {
1121 compatible = "rockchip,rk3588-qos", "syscon";
1122 reg = <0x0 0xfdf63000 0x0 0x20>;
1123 };
1124
1125 qos_av1: qos@fdf64000 {
1126 compatible = "rockchip,rk3588-qos", "syscon";
1127 reg = <0x0 0xfdf64000 0x0 0x20>;
1128 };
1129
1130 qos_iep: qos@fdf66000 {
1131 compatible = "rockchip,rk3588-qos", "syscon";
1132 reg = <0x0 0xfdf66000 0x0 0x20>;
1133 };
1134
1135 qos_jpeg_dec: qos@fdf66200 {
1136 compatible = "rockchip,rk3588-qos", "syscon";
1137 reg = <0x0 0xfdf66200 0x0 0x20>;
1138 };
1139
1140 qos_jpeg_enc0: qos@fdf66400 {
1141 compatible = "rockchip,rk3588-qos", "syscon";
1142 reg = <0x0 0xfdf66400 0x0 0x20>;
1143 };
1144
1145 qos_jpeg_enc1: qos@fdf66600 {
1146 compatible = "rockchip,rk3588-qos", "syscon";
1147 reg = <0x0 0xfdf66600 0x0 0x20>;
1148 };
1149
1150 qos_jpeg_enc2: qos@fdf66800 {
1151 compatible = "rockchip,rk3588-qos", "syscon";
1152 reg = <0x0 0xfdf66800 0x0 0x20>;
1153 };
1154
1155 qos_jpeg_enc3: qos@fdf66a00 {
1156 compatible = "rockchip,rk3588-qos", "syscon";
1157 reg = <0x0 0xfdf66a00 0x0 0x20>;
1158 };
1159
1160 qos_rga2_mro: qos@fdf66c00 {
1161 compatible = "rockchip,rk3588-qos", "syscon";
1162 reg = <0x0 0xfdf66c00 0x0 0x20>;
1163 };
1164
1165 qos_rga2_mwo: qos@fdf66e00 {
1166 compatible = "rockchip,rk3588-qos", "syscon";
1167 reg = <0x0 0xfdf66e00 0x0 0x20>;
1168 };
1169
1170 qos_rga3_0: qos@fdf67000 {
1171 compatible = "rockchip,rk3588-qos", "syscon";
1172 reg = <0x0 0xfdf67000 0x0 0x20>;
1173 };
1174
1175 qos_vdpu: qos@fdf67200 {
1176 compatible = "rockchip,rk3588-qos", "syscon";
1177 reg = <0x0 0xfdf67200 0x0 0x20>;
1178 };
1179
1180 qos_npu1: qos@fdf70000 {
1181 compatible = "rockchip,rk3588-qos", "syscon";
1182 reg = <0x0 0xfdf70000 0x0 0x20>;
1183 };
1184
1185 qos_npu2: qos@fdf71000 {
1186 compatible = "rockchip,rk3588-qos", "syscon";
1187 reg = <0x0 0xfdf71000 0x0 0x20>;
1188 };
1189
1190 qos_npu0_mwr: qos@fdf72000 {
1191 compatible = "rockchip,rk3588-qos", "syscon";
1192 reg = <0x0 0xfdf72000 0x0 0x20>;
1193 };
1194
1195 qos_npu0_mro: qos@fdf72200 {
1196 compatible = "rockchip,rk3588-qos", "syscon";
1197 reg = <0x0 0xfdf72200 0x0 0x20>;
1198 };
1199
1200 qos_mcu_npu: qos@fdf72400 {
1201 compatible = "rockchip,rk3588-qos", "syscon";
1202 reg = <0x0 0xfdf72400 0x0 0x20>;
1203 };
1204
1205 qos_hdcp0: qos@fdf80000 {
1206 compatible = "rockchip,rk3588-qos", "syscon";
1207 reg = <0x0 0xfdf80000 0x0 0x20>;
1208 };
1209
1210 qos_hdcp1: qos@fdf81000 {
1211 compatible = "rockchip,rk3588-qos", "syscon";
1212 reg = <0x0 0xfdf81000 0x0 0x20>;
1213 };
1214
1215 qos_hdmirx: qos@fdf81200 {
1216 compatible = "rockchip,rk3588-qos", "syscon";
1217 reg = <0x0 0xfdf81200 0x0 0x20>;
1218 };
1219
1220 qos_vop_m0: qos@fdf82000 {
1221 compatible = "rockchip,rk3588-qos", "syscon";
1222 reg = <0x0 0xfdf82000 0x0 0x20>;
1223 };
1224
1225 qos_vop_m1: qos@fdf82200 {
1226 compatible = "rockchip,rk3588-qos", "syscon";
1227 reg = <0x0 0xfdf82200 0x0 0x20>;
1228 };
1229
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]1230 pcie2x1l1: pcie@fe180000 {
1231 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1232 bus-range = <0x30 0x3f>;
1233 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1234 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1235 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1236 clock-names = "aclk_mst", "aclk_slv",
1237 "aclk_dbi", "pclk",
1238 "aux", "pipe";
1239 device_type = "pci";
1240 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
1241 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
1242 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
1243 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
1244 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
1245 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1246 #interrupt-cells = <1>;
1247 interrupt-map-mask = <0 0 0 7>;
1248 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1249 <0 0 0 2 &pcie2x1l1_intc 1>,
1250 <0 0 0 3 &pcie2x1l1_intc 2>,
1251 <0 0 0 4 &pcie2x1l1_intc 3>;
1252 linux,pci-domain = <3>;
1253 max-link-speed = <2>;
1254 msi-map = <0x3000 &its0 0x3000 0x1000>;
1255 num-lanes = <1>;
1256 phys = <&combphy2_psu PHY_TYPE_PCIE>;
1257 phy-names = "pcie-phy";
1258 power-domains = <&power RK3588_PD_PCIE>;
1259 ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
1260 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
1261 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
1262 reg = <0xa 0x40c00000 0x0 0x00400000>,
1263 <0x0 0xfe180000 0x0 0x00010000>,
1264 <0x0 0xf3000000 0x0 0x00100000>;
1265 reg-names = "dbi", "apb", "config";
1266 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1267 reset-names = "pwr", "pipe";
1268 #address-cells = <3>;
1269 #size-cells = <2>;
1270 status = "disabled";
1271
1272 pcie2x1l1_intc: legacy-interrupt-controller {
1273 interrupt-controller;
1274 #address-cells = <0>;
1275 #interrupt-cells = <1>;
1276 interrupt-parent = <&gic>;
1277 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
1278 };
1279 };
1280
1281 pcie2x1l2: pcie@fe190000 {
1282 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
1283 bus-range = <0x40 0x4f>;
1284 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1285 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1286 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1287 clock-names = "aclk_mst", "aclk_slv",
1288 "aclk_dbi", "pclk",
1289 "aux", "pipe";
1290 device_type = "pci";
1291 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
1292 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
1293 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
1294 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
1295 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
1296 interrupt-names = "sys", "pmc", "msg", "legacy", "err";
1297 #interrupt-cells = <1>;
1298 interrupt-map-mask = <0 0 0 7>;
1299 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1300 <0 0 0 2 &pcie2x1l2_intc 1>,
1301 <0 0 0 3 &pcie2x1l2_intc 2>,
1302 <0 0 0 4 &pcie2x1l2_intc 3>;
1303 linux,pci-domain = <4>;
1304 max-link-speed = <2>;
1305 msi-map = <0x4000 &its0 0x4000 0x1000>;
1306 num-lanes = <1>;
1307 phys = <&combphy0_ps PHY_TYPE_PCIE>;
1308 phy-names = "pcie-phy";
1309 power-domains = <&power RK3588_PD_PCIE>;
1310 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
1311 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
1312 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
1313 reg = <0xa 0x41000000 0x0 0x00400000>,
1314 <0x0 0xfe190000 0x0 0x00010000>,
1315 <0x0 0xf4000000 0x0 0x00100000>;
1316 reg-names = "dbi", "apb", "config";
1317 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1318 reset-names = "pwr", "pipe";
1319 #address-cells = <3>;
1320 #size-cells = <2>;
1321 status = "disabled";
1322
1323 pcie2x1l2_intc: legacy-interrupt-controller {
1324 interrupt-controller;
1325 #address-cells = <0>;
1326 #interrupt-cells = <1>;
1327 interrupt-parent = <&gic>;
1328 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
1329 };
1330 };
1331
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1332 gmac1: ethernet@fe1c0000 {
1333 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1334 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1335 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1336 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1337 interrupt-names = "macirq", "eth_wake_irq";
1338 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1339 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1340 <&cru CLK_GMAC1_PTP_REF>;
1341 clock-names = "stmmaceth", "clk_mac_ref",
1342 "pclk_mac", "aclk_mac",
1343 "ptp_ref";
1344 power-domains = <&power RK3588_PD_GMAC>;
1345 resets = <&cru SRST_A_GMAC1>;
1346 reset-names = "stmmaceth";
1347 rockchip,grf = <&sys_grf>;
1348 rockchip,php-grf = <&php_grf>;
1349 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1350 snps,mixed-burst;
1351 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1352 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1353 snps,tso;
1354 status = "disabled";
1355
1356 mdio1: mdio {
1357 compatible = "snps,dwmac-mdio";
1358 #address-cells = <0x1>;
1359 #size-cells = <0x0>;
1360 };
1361
1362 gmac1_stmmac_axi_setup: stmmac-axi-config {
1363 snps,blen = <0 0 0 0 16 8 4>;
1364 snps,wr_osr_lmt = <4>;
1365 snps,rd_osr_lmt = <8>;
1366 };
1367
1368 gmac1_mtl_rx_setup: rx-queues-config {
1369 snps,rx-queues-to-use = <2>;
1370 queue0 {};
1371 queue1 {};
1372 };
1373
1374 gmac1_mtl_tx_setup: tx-queues-config {
1375 snps,tx-queues-to-use = <2>;
1376 queue0 {};
1377 queue1 {};
1378 };
1379 };
1380
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]1381 sata0: sata@fe210000 {
1382 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1383 reg = <0 0xfe210000 0 0x1000>;
1384 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
1385 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1386 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1387 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1388 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1389 ports-implemented = <0x1>;
1390 #address-cells = <1>;
1391 #size-cells = <0>;
1392 status = "disabled";
1393
1394 sata-port@0 {
1395 reg = <0>;
1396 hba-port-cap = <HBA_PORT_FBSCP>;
1397 phys = <&combphy0_ps PHY_TYPE_SATA>;
1398 phy-names = "sata-phy";
1399 snps,rx-ts-max = <32>;
1400 snps,tx-ts-max = <32>;
1401 };
1402 };
1403
1404 sata2: sata@fe230000 {
1405 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
1406 reg = <0 0xfe230000 0 0x1000>;
1407 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
1408 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1409 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1410 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1411 clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
1412 ports-implemented = <0x1>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1415 status = "disabled";
1416
1417 sata-port@0 {
1418 reg = <0>;
1419 hba-port-cap = <HBA_PORT_FBSCP>;
1420 phys = <&combphy2_psu PHY_TYPE_SATA>;
1421 phy-names = "sata-phy";
1422 snps,rx-ts-max = <32>;
1423 snps,tx-ts-max = <32>;
1424 };
1425 };
1426
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000[diff] [blame]1427 sdmmc: mmc@fe2c0000 {
1428 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1429 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1430 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1431 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1432 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1433 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1434 fifo-depth = <0x100>;
1435 max-frequency = <200000000>;
1436 pinctrl-names = "default";
1437 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1438 power-domains = <&power RK3588_PD_SDMMC>;
1439 status = "disabled";
1440 };
1441
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]1442 sdio: mmc@fe2d0000 {
1443 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1444 reg = <0x00 0xfe2d0000 0x00 0x4000>;
1445 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
1446 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1447 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1448 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1449 fifo-depth = <0x100>;
1450 max-frequency = <200000000>;
1451 pinctrl-names = "default";
1452 pinctrl-0 = <&sdiom1_pins>;
1453 power-domains = <&power RK3588_PD_SDIO>;
1454 status = "disabled";
1455 };
1456
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1457 sdhci: mmc@fe2e0000 {
1458 compatible = "rockchip,rk3588-dwcmshc";
1459 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1460 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1461 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1462 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1463 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1464 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1465 <&cru TMCLK_EMMC>;
1466 clock-names = "core", "bus", "axi", "block", "timer";
1467 max-frequency = <200000000>;
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]1468 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1469 <&emmc_cmd>, <&emmc_data_strobe>;
1470 pinctrl-names = "default";
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1471 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1472 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1473 <&cru SRST_T_EMMC>;
1474 reset-names = "core", "bus", "axi", "block", "timer";
1475 status = "disabled";
1476 };
1477
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]1478 i2s0_8ch: i2s@fe470000 {
1479 compatible = "rockchip,rk3588-i2s-tdm";
1480 reg = <0x0 0xfe470000 0x0 0x1000>;
1481 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1482 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1483 clock-names = "mclk_tx", "mclk_rx", "hclk";
1484 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1485 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1486 dmas = <&dmac0 0>, <&dmac0 1>;
1487 dma-names = "tx", "rx";
1488 power-domains = <&power RK3588_PD_AUDIO>;
1489 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1490 reset-names = "tx-m", "rx-m";
1491 rockchip,trcm-sync-tx-only;
1492 pinctrl-names = "default";
1493 pinctrl-0 = <&i2s0_lrck
1494 &i2s0_sclk
1495 &i2s0_sdi0
1496 &i2s0_sdi1
1497 &i2s0_sdi2
1498 &i2s0_sdi3
1499 &i2s0_sdo0
1500 &i2s0_sdo1
1501 &i2s0_sdo2
1502 &i2s0_sdo3>;
1503 #sound-dai-cells = <0>;
1504 status = "disabled";
1505 };
1506
1507 i2s1_8ch: i2s@fe480000 {
1508 compatible = "rockchip,rk3588-i2s-tdm";
1509 reg = <0x0 0xfe480000 0x0 0x1000>;
1510 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1511 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1512 clock-names = "mclk_tx", "mclk_rx", "hclk";
1513 dmas = <&dmac0 2>, <&dmac0 3>;
1514 dma-names = "tx", "rx";
1515 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1516 reset-names = "tx-m", "rx-m";
1517 rockchip,trcm-sync-tx-only;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&i2s1m0_lrck
1520 &i2s1m0_sclk
1521 &i2s1m0_sdi0
1522 &i2s1m0_sdi1
1523 &i2s1m0_sdi2
1524 &i2s1m0_sdi3
1525 &i2s1m0_sdo0
1526 &i2s1m0_sdo1
1527 &i2s1m0_sdo2
1528 &i2s1m0_sdo3>;
1529 #sound-dai-cells = <0>;
1530 status = "disabled";
1531 };
1532
1533 i2s2_2ch: i2s@fe490000 {
1534 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1535 reg = <0x0 0xfe490000 0x0 0x1000>;
1536 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1537 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1538 clock-names = "i2s_clk", "i2s_hclk";
1539 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1540 assigned-clock-parents = <&cru PLL_AUPLL>;
1541 dmas = <&dmac1 0>, <&dmac1 1>;
1542 dma-names = "tx", "rx";
1543 power-domains = <&power RK3588_PD_AUDIO>;
1544 rockchip,trcm-sync-tx-only;
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&i2s2m1_lrck
1547 &i2s2m1_sclk
1548 &i2s2m1_sdi
1549 &i2s2m1_sdo>;
1550 #sound-dai-cells = <0>;
1551 status = "disabled";
1552 };
1553
1554 i2s3_2ch: i2s@fe4a0000 {
1555 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1556 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1557 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1558 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1559 clock-names = "i2s_clk", "i2s_hclk";
1560 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1561 assigned-clock-parents = <&cru PLL_AUPLL>;
1562 dmas = <&dmac1 2>, <&dmac1 3>;
1563 dma-names = "tx", "rx";
1564 power-domains = <&power RK3588_PD_AUDIO>;
1565 rockchip,trcm-sync-tx-only;
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&i2s3_lrck
1568 &i2s3_sclk
1569 &i2s3_sdi
1570 &i2s3_sdo>;
1571 #sound-dai-cells = <0>;
1572 status = "disabled";
1573 };
1574
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1575 gic: interrupt-controller@fe600000 {
1576 compatible = "arm,gic-v3";
1577 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1578 <0x0 0xfe680000 0 0x100000>; /* GICR */
1579 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1580 interrupt-controller;
1581 mbi-alias = <0x0 0xfe610000>;
1582 mbi-ranges = <424 56>;
1583 msi-controller;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]1584 ranges;
1585 #address-cells = <2>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1586 #interrupt-cells = <4>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]1587 #size-cells = <2>;
1588
1589 its0: msi-controller@fe640000 {
1590 compatible = "arm,gic-v3-its";
1591 reg = <0x0 0xfe640000 0x0 0x20000>;
1592 msi-controller;
1593 #msi-cells = <1>;
1594 };
1595
1596 its1: msi-controller@fe660000 {
1597 compatible = "arm,gic-v3-its";
1598 reg = <0x0 0xfe660000 0x0 0x20000>;
1599 msi-controller;
1600 #msi-cells = <1>;
1601 };
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1602
1603 ppi-partitions {
1604 ppi_partition0: interrupt-partition-0 {
1605 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1606 };
1607
1608 ppi_partition1: interrupt-partition-1 {
1609 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1610 };
1611 };
1612 };
1613
1614 dmac0: dma-controller@fea10000 {
1615 compatible = "arm,pl330", "arm,primecell";
1616 reg = <0x0 0xfea10000 0x0 0x4000>;
1617 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1618 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1619 arm,pl330-periph-burst;
1620 clocks = <&cru ACLK_DMAC0>;
1621 clock-names = "apb_pclk";
1622 #dma-cells = <1>;
1623 };
1624
1625 dmac1: dma-controller@fea30000 {
1626 compatible = "arm,pl330", "arm,primecell";
1627 reg = <0x0 0xfea30000 0x0 0x4000>;
1628 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1629 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1630 arm,pl330-periph-burst;
1631 clocks = <&cru ACLK_DMAC1>;
1632 clock-names = "apb_pclk";
1633 #dma-cells = <1>;
1634 };
1635
1636 i2c1: i2c@fea90000 {
1637 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1638 reg = <0x0 0xfea90000 0x0 0x1000>;
1639 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1640 clock-names = "i2c", "pclk";
1641 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1642 pinctrl-0 = <&i2c1m0_xfer>;
1643 pinctrl-names = "default";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1646 status = "disabled";
1647 };
1648
1649 i2c2: i2c@feaa0000 {
1650 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1651 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1652 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1653 clock-names = "i2c", "pclk";
1654 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1655 pinctrl-0 = <&i2c2m0_xfer>;
1656 pinctrl-names = "default";
1657 #address-cells = <1>;
1658 #size-cells = <0>;
1659 status = "disabled";
1660 };
1661
1662 i2c3: i2c@feab0000 {
1663 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1664 reg = <0x0 0xfeab0000 0x0 0x1000>;
1665 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1666 clock-names = "i2c", "pclk";
1667 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1668 pinctrl-0 = <&i2c3m0_xfer>;
1669 pinctrl-names = "default";
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1672 status = "disabled";
1673 };
1674
1675 i2c4: i2c@feac0000 {
1676 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1677 reg = <0x0 0xfeac0000 0x0 0x1000>;
1678 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1679 clock-names = "i2c", "pclk";
1680 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1681 pinctrl-0 = <&i2c4m0_xfer>;
1682 pinctrl-names = "default";
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685 status = "disabled";
1686 };
1687
1688 i2c5: i2c@fead0000 {
1689 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1690 reg = <0x0 0xfead0000 0x0 0x1000>;
1691 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1692 clock-names = "i2c", "pclk";
1693 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1694 pinctrl-0 = <&i2c5m0_xfer>;
1695 pinctrl-names = "default";
1696 #address-cells = <1>;
1697 #size-cells = <0>;
1698 status = "disabled";
1699 };
1700
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]1701 timer0: timer@feae0000 {
1702 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1703 reg = <0x0 0xfeae0000 0x0 0x20>;
1704 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1705 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1706 clock-names = "pclk", "timer";
1707 };
1708
1709 wdt: watchdog@feaf0000 {
1710 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1711 reg = <0x0 0xfeaf0000 0x0 0x100>;
1712 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1713 clock-names = "tclk", "pclk";
1714 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1715 };
1716
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1717 spi0: spi@feb00000 {
1718 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1719 reg = <0x0 0xfeb00000 0x0 0x1000>;
1720 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1721 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1722 clock-names = "spiclk", "apb_pclk";
1723 dmas = <&dmac0 14>, <&dmac0 15>;
1724 dma-names = "tx", "rx";
1725 num-cs = <2>;
1726 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1727 pinctrl-names = "default";
1728 #address-cells = <1>;
1729 #size-cells = <0>;
1730 status = "disabled";
1731 };
1732
1733 spi1: spi@feb10000 {
1734 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1735 reg = <0x0 0xfeb10000 0x0 0x1000>;
1736 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1737 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1738 clock-names = "spiclk", "apb_pclk";
1739 dmas = <&dmac0 16>, <&dmac0 17>;
1740 dma-names = "tx", "rx";
1741 num-cs = <2>;
1742 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1743 pinctrl-names = "default";
1744 #address-cells = <1>;
1745 #size-cells = <0>;
1746 status = "disabled";
1747 };
1748
1749 spi2: spi@feb20000 {
1750 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1751 reg = <0x0 0xfeb20000 0x0 0x1000>;
1752 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1753 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1754 clock-names = "spiclk", "apb_pclk";
1755 dmas = <&dmac1 15>, <&dmac1 16>;
1756 dma-names = "tx", "rx";
1757 num-cs = <2>;
1758 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1759 pinctrl-names = "default";
1760 #address-cells = <1>;
1761 #size-cells = <0>;
1762 status = "disabled";
1763 };
1764
1765 spi3: spi@feb30000 {
1766 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1767 reg = <0x0 0xfeb30000 0x0 0x1000>;
1768 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1769 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1770 clock-names = "spiclk", "apb_pclk";
1771 dmas = <&dmac1 17>, <&dmac1 18>;
1772 dma-names = "tx", "rx";
1773 num-cs = <2>;
1774 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1775 pinctrl-names = "default";
1776 #address-cells = <1>;
1777 #size-cells = <0>;
1778 status = "disabled";
1779 };
1780
1781 uart1: serial@feb40000 {
1782 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1783 reg = <0x0 0xfeb40000 0x0 0x100>;
1784 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1785 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1786 clock-names = "baudclk", "apb_pclk";
1787 dmas = <&dmac0 8>, <&dmac0 9>;
1788 dma-names = "tx", "rx";
1789 pinctrl-0 = <&uart1m1_xfer>;
1790 pinctrl-names = "default";
1791 reg-io-width = <4>;
1792 reg-shift = <2>;
1793 status = "disabled";
1794 };
1795
1796 uart2: serial@feb50000 {
1797 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1798 reg = <0x0 0xfeb50000 0x0 0x100>;
1799 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1800 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1801 clock-names = "baudclk", "apb_pclk";
1802 dmas = <&dmac0 10>, <&dmac0 11>;
1803 dma-names = "tx", "rx";
1804 pinctrl-0 = <&uart2m1_xfer>;
1805 pinctrl-names = "default";
1806 reg-io-width = <4>;
1807 reg-shift = <2>;
1808 status = "disabled";
1809 };
1810
1811 uart3: serial@feb60000 {
1812 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1813 reg = <0x0 0xfeb60000 0x0 0x100>;
1814 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1815 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1816 clock-names = "baudclk", "apb_pclk";
1817 dmas = <&dmac0 12>, <&dmac0 13>;
1818 dma-names = "tx", "rx";
1819 pinctrl-0 = <&uart3m1_xfer>;
1820 pinctrl-names = "default";
1821 reg-io-width = <4>;
1822 reg-shift = <2>;
1823 status = "disabled";
1824 };
1825
1826 uart4: serial@feb70000 {
1827 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1828 reg = <0x0 0xfeb70000 0x0 0x100>;
1829 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1830 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1831 clock-names = "baudclk", "apb_pclk";
1832 dmas = <&dmac1 9>, <&dmac1 10>;
1833 dma-names = "tx", "rx";
1834 pinctrl-0 = <&uart4m1_xfer>;
1835 pinctrl-names = "default";
1836 reg-io-width = <4>;
1837 reg-shift = <2>;
1838 status = "disabled";
1839 };
1840
1841 uart5: serial@feb80000 {
1842 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1843 reg = <0x0 0xfeb80000 0x0 0x100>;
1844 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1845 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1846 clock-names = "baudclk", "apb_pclk";
1847 dmas = <&dmac1 11>, <&dmac1 12>;
1848 dma-names = "tx", "rx";
1849 pinctrl-0 = <&uart5m1_xfer>;
1850 pinctrl-names = "default";
1851 reg-io-width = <4>;
1852 reg-shift = <2>;
1853 status = "disabled";
1854 };
1855
1856 uart6: serial@feb90000 {
1857 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1858 reg = <0x0 0xfeb90000 0x0 0x100>;
1859 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1860 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1861 clock-names = "baudclk", "apb_pclk";
1862 dmas = <&dmac1 13>, <&dmac1 14>;
1863 dma-names = "tx", "rx";
1864 pinctrl-0 = <&uart6m1_xfer>;
1865 pinctrl-names = "default";
1866 reg-io-width = <4>;
1867 reg-shift = <2>;
1868 status = "disabled";
1869 };
1870
1871 uart7: serial@feba0000 {
1872 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1873 reg = <0x0 0xfeba0000 0x0 0x100>;
1874 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1875 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1876 clock-names = "baudclk", "apb_pclk";
1877 dmas = <&dmac2 7>, <&dmac2 8>;
1878 dma-names = "tx", "rx";
1879 pinctrl-0 = <&uart7m1_xfer>;
1880 pinctrl-names = "default";
1881 reg-io-width = <4>;
1882 reg-shift = <2>;
1883 status = "disabled";
1884 };
1885
1886 uart8: serial@febb0000 {
1887 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1888 reg = <0x0 0xfebb0000 0x0 0x100>;
1889 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1890 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1891 clock-names = "baudclk", "apb_pclk";
1892 dmas = <&dmac2 9>, <&dmac2 10>;
1893 dma-names = "tx", "rx";
1894 pinctrl-0 = <&uart8m1_xfer>;
1895 pinctrl-names = "default";
1896 reg-io-width = <4>;
1897 reg-shift = <2>;
1898 status = "disabled";
1899 };
1900
1901 uart9: serial@febc0000 {
1902 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1903 reg = <0x0 0xfebc0000 0x0 0x100>;
1904 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1905 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1906 clock-names = "baudclk", "apb_pclk";
1907 dmas = <&dmac2 11>, <&dmac2 12>;
1908 dma-names = "tx", "rx";
1909 pinctrl-0 = <&uart9m1_xfer>;
1910 pinctrl-names = "default";
1911 reg-io-width = <4>;
1912 reg-shift = <2>;
1913 status = "disabled";
1914 };
1915
1916 pwm4: pwm@febd0000 {
1917 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1918 reg = <0x0 0xfebd0000 0x0 0x10>;
1919 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1920 clock-names = "pwm", "pclk";
1921 pinctrl-0 = <&pwm4m0_pins>;
1922 pinctrl-names = "default";
1923 #pwm-cells = <3>;
1924 status = "disabled";
1925 };
1926
1927 pwm5: pwm@febd0010 {
1928 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1929 reg = <0x0 0xfebd0010 0x0 0x10>;
1930 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1931 clock-names = "pwm", "pclk";
1932 pinctrl-0 = <&pwm5m0_pins>;
1933 pinctrl-names = "default";
1934 #pwm-cells = <3>;
1935 status = "disabled";
1936 };
1937
1938 pwm6: pwm@febd0020 {
1939 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1940 reg = <0x0 0xfebd0020 0x0 0x10>;
1941 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1942 clock-names = "pwm", "pclk";
1943 pinctrl-0 = <&pwm6m0_pins>;
1944 pinctrl-names = "default";
1945 #pwm-cells = <3>;
1946 status = "disabled";
1947 };
1948
1949 pwm7: pwm@febd0030 {
1950 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1951 reg = <0x0 0xfebd0030 0x0 0x10>;
1952 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1953 clock-names = "pwm", "pclk";
1954 pinctrl-0 = <&pwm7m0_pins>;
1955 pinctrl-names = "default";
1956 #pwm-cells = <3>;
1957 status = "disabled";
1958 };
1959
1960 pwm8: pwm@febe0000 {
1961 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1962 reg = <0x0 0xfebe0000 0x0 0x10>;
1963 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1964 clock-names = "pwm", "pclk";
1965 pinctrl-0 = <&pwm8m0_pins>;
1966 pinctrl-names = "default";
1967 #pwm-cells = <3>;
1968 status = "disabled";
1969 };
1970
1971 pwm9: pwm@febe0010 {
1972 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1973 reg = <0x0 0xfebe0010 0x0 0x10>;
1974 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1975 clock-names = "pwm", "pclk";
1976 pinctrl-0 = <&pwm9m0_pins>;
1977 pinctrl-names = "default";
1978 #pwm-cells = <3>;
1979 status = "disabled";
1980 };
1981
1982 pwm10: pwm@febe0020 {
1983 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1984 reg = <0x0 0xfebe0020 0x0 0x10>;
1985 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1986 clock-names = "pwm", "pclk";
1987 pinctrl-0 = <&pwm10m0_pins>;
1988 pinctrl-names = "default";
1989 #pwm-cells = <3>;
1990 status = "disabled";
1991 };
1992
1993 pwm11: pwm@febe0030 {
1994 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1995 reg = <0x0 0xfebe0030 0x0 0x10>;
1996 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1997 clock-names = "pwm", "pclk";
1998 pinctrl-0 = <&pwm11m0_pins>;
1999 pinctrl-names = "default";
2000 #pwm-cells = <3>;
2001 status = "disabled";
2002 };
2003
2004 pwm12: pwm@febf0000 {
2005 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2006 reg = <0x0 0xfebf0000 0x0 0x10>;
2007 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2008 clock-names = "pwm", "pclk";
2009 pinctrl-0 = <&pwm12m0_pins>;
2010 pinctrl-names = "default";
2011 #pwm-cells = <3>;
2012 status = "disabled";
2013 };
2014
2015 pwm13: pwm@febf0010 {
2016 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2017 reg = <0x0 0xfebf0010 0x0 0x10>;
2018 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2019 clock-names = "pwm", "pclk";
2020 pinctrl-0 = <&pwm13m0_pins>;
2021 pinctrl-names = "default";
2022 #pwm-cells = <3>;
2023 status = "disabled";
2024 };
2025
2026 pwm14: pwm@febf0020 {
2027 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2028 reg = <0x0 0xfebf0020 0x0 0x10>;
2029 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2030 clock-names = "pwm", "pclk";
2031 pinctrl-0 = <&pwm14m0_pins>;
2032 pinctrl-names = "default";
2033 #pwm-cells = <3>;
2034 status = "disabled";
2035 };
2036
2037 pwm15: pwm@febf0030 {
2038 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
2039 reg = <0x0 0xfebf0030 0x0 0x10>;
2040 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2041 clock-names = "pwm", "pclk";
2042 pinctrl-0 = <&pwm15m0_pins>;
2043 pinctrl-names = "default";
2044 #pwm-cells = <3>;
2045 status = "disabled";
2046 };
2047
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]2048 tsadc: tsadc@fec00000 {
2049 compatible = "rockchip,rk3588-tsadc";
2050 reg = <0x0 0xfec00000 0x0 0x400>;
2051 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
2052 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2053 clock-names = "tsadc", "apb_pclk";
2054 assigned-clocks = <&cru CLK_TSADC>;
2055 assigned-clock-rates = <2000000>;
2056 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2057 reset-names = "tsadc-apb", "tsadc";
2058 rockchip,hw-tshut-temp = <120000>;
2059 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2060 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2061 pinctrl-0 = <&tsadc_gpio_func>;
2062 pinctrl-1 = <&tsadc_shut>;
2063 pinctrl-names = "gpio", "otpout";
2064 #thermal-sensor-cells = <1>;
2065 status = "disabled";
2066 };
2067
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]2068 saradc: adc@fec10000 {
2069 compatible = "rockchip,rk3588-saradc";
2070 reg = <0x0 0xfec10000 0x0 0x10000>;
2071 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
2072 #io-channel-cells = <1>;
2073 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2074 clock-names = "saradc", "apb_pclk";
2075 resets = <&cru SRST_P_SARADC>;
2076 reset-names = "saradc-apb";
2077 status = "disabled";
2078 };
2079
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]2080 i2c6: i2c@fec80000 {
2081 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2082 reg = <0x0 0xfec80000 0x0 0x1000>;
2083 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2084 clock-names = "i2c", "pclk";
2085 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
2086 pinctrl-0 = <&i2c6m0_xfer>;
2087 pinctrl-names = "default";
2088 #address-cells = <1>;
2089 #size-cells = <0>;
2090 status = "disabled";
2091 };
2092
2093 i2c7: i2c@fec90000 {
2094 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2095 reg = <0x0 0xfec90000 0x0 0x1000>;
2096 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2097 clock-names = "i2c", "pclk";
2098 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
2099 pinctrl-0 = <&i2c7m0_xfer>;
2100 pinctrl-names = "default";
2101 #address-cells = <1>;
2102 #size-cells = <0>;
2103 status = "disabled";
2104 };
2105
2106 i2c8: i2c@feca0000 {
2107 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
2108 reg = <0x0 0xfeca0000 0x0 0x1000>;
2109 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2110 clock-names = "i2c", "pclk";
2111 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
2112 pinctrl-0 = <&i2c8m0_xfer>;
2113 pinctrl-names = "default";
2114 #address-cells = <1>;
2115 #size-cells = <0>;
2116 status = "disabled";
2117 };
2118
2119 spi4: spi@fecb0000 {
2120 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
2121 reg = <0x0 0xfecb0000 0x0 0x1000>;
2122 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
2123 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2124 clock-names = "spiclk", "apb_pclk";
2125 dmas = <&dmac2 13>, <&dmac2 14>;
2126 dma-names = "tx", "rx";
2127 num-cs = <2>;
2128 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2129 pinctrl-names = "default";
2130 #address-cells = <1>;
2131 #size-cells = <0>;
2132 status = "disabled";
2133 };
2134
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame]2135 otp: efuse@fecc0000 {
2136 compatible = "rockchip,rk3588-otp";
2137 reg = <0x0 0xfecc0000 0x0 0x400>;
2138 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2139 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2140 clock-names = "otp", "apb_pclk", "phy", "arb";
2141 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2142 <&cru SRST_OTPC_ARB>;
2143 reset-names = "otp", "apb", "arb";
2144 #address-cells = <1>;
2145 #size-cells = <1>;
2146
2147 cpu_code: cpu-code@2 {
2148 reg = <0x02 0x2>;
2149 };
2150
2151 otp_id: id@7 {
2152 reg = <0x07 0x10>;
2153 };
2154
2155 cpub0_leakage: cpu-leakage@17 {
2156 reg = <0x17 0x1>;
2157 };
2158
2159 cpub1_leakage: cpu-leakage@18 {
2160 reg = <0x18 0x1>;
2161 };
2162
2163 cpul_leakage: cpu-leakage@19 {
2164 reg = <0x19 0x1>;
2165 };
2166
2167 log_leakage: log-leakage@1a {
2168 reg = <0x1a 0x1>;
2169 };
2170
2171 gpu_leakage: gpu-leakage@1b {
2172 reg = <0x1b 0x1>;
2173 };
2174
2175 otp_cpu_version: cpu-version@1c {
2176 reg = <0x1c 0x1>;
2177 bits = <3 3>;
2178 };
2179
2180 npu_leakage: npu-leakage@28 {
2181 reg = <0x28 0x1>;
2182 };
2183
2184 codec_leakage: codec-leakage@29 {
2185 reg = <0x29 0x1>;
2186 };
2187 };
2188
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]2189 dmac2: dma-controller@fed10000 {
2190 compatible = "arm,pl330", "arm,primecell";
2191 reg = <0x0 0xfed10000 0x0 0x4000>;
2192 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
2193 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
2194 arm,pl330-periph-burst;
2195 clocks = <&cru ACLK_DMAC2>;
2196 clock-names = "apb_pclk";
2197 #dma-cells = <1>;
2198 };
2199
FUKAUMI Naoki61315172023-09-05 20:47:35 +0900[diff] [blame]2200 combphy0_ps: phy@fee00000 {
2201 compatible = "rockchip,rk3588-naneng-combphy";
2202 reg = <0x0 0xfee00000 0x0 0x100>;
2203 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2204 <&cru PCLK_PHP_ROOT>;
2205 clock-names = "ref", "apb", "pipe";
2206 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2207 assigned-clock-rates = <100000000>;
2208 #phy-cells = <1>;
2209 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2210 reset-names = "phy", "apb";
2211 rockchip,pipe-grf = <&php_grf>;
2212 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
2213 status = "disabled";
2214 };
2215
2216 combphy2_psu: phy@fee20000 {
2217 compatible = "rockchip,rk3588-naneng-combphy";
2218 reg = <0x0 0xfee20000 0x0 0x100>;
2219 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2220 <&cru PCLK_PHP_ROOT>;
2221 clock-names = "ref", "apb", "pipe";
2222 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2223 assigned-clock-rates = <100000000>;
2224 #phy-cells = <1>;
2225 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2226 reset-names = "phy", "apb";
2227 rockchip,pipe-grf = <&php_grf>;
2228 rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
2229 status = "disabled";
2230 };
2231
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]2232 system_sram2: sram@ff001000 {
2233 compatible = "mmio-sram";
2234 reg = <0x0 0xff001000 0x0 0xef000>;
2235 ranges = <0x0 0x0 0xff001000 0xef000>;
2236 #address-cells = <1>;
2237 #size-cells = <1>;
2238 };
2239
2240 pinctrl: pinctrl {
2241 compatible = "rockchip,rk3588-pinctrl";
2242 ranges;
2243 rockchip,grf = <&ioc>;
2244 #address-cells = <2>;
2245 #size-cells = <2>;
2246
2247 gpio0: gpio@fd8a0000 {
2248 compatible = "rockchip,gpio-bank";
2249 reg = <0x0 0xfd8a0000 0x0 0x100>;
2250 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
2251 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2252 gpio-controller;
2253 gpio-ranges = <&pinctrl 0 0 32>;
2254 interrupt-controller;
2255 #gpio-cells = <2>;
2256 #interrupt-cells = <2>;
2257 };
2258
2259 gpio1: gpio@fec20000 {
2260 compatible = "rockchip,gpio-bank";
2261 reg = <0x0 0xfec20000 0x0 0x100>;
2262 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
2263 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2264 gpio-controller;
2265 gpio-ranges = <&pinctrl 0 32 32>;
2266 interrupt-controller;
2267 #gpio-cells = <2>;
2268 #interrupt-cells = <2>;
2269 };
2270
2271 gpio2: gpio@fec30000 {
2272 compatible = "rockchip,gpio-bank";
2273 reg = <0x0 0xfec30000 0x0 0x100>;
2274 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
2275 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2276 gpio-controller;
2277 gpio-ranges = <&pinctrl 0 64 32>;
2278 interrupt-controller;
2279 #gpio-cells = <2>;
2280 #interrupt-cells = <2>;
2281 };
2282
2283 gpio3: gpio@fec40000 {
2284 compatible = "rockchip,gpio-bank";
2285 reg = <0x0 0xfec40000 0x0 0x100>;
2286 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
2287 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2288 gpio-controller;
2289 gpio-ranges = <&pinctrl 0 96 32>;
2290 interrupt-controller;
2291 #gpio-cells = <2>;
2292 #interrupt-cells = <2>;
2293 };
2294
2295 gpio4: gpio@fec50000 {
2296 compatible = "rockchip,gpio-bank";
2297 reg = <0x0 0xfec50000 0x0 0x100>;
2298 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
2299 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2300 gpio-controller;
2301 gpio-ranges = <&pinctrl 0 128 32>;
2302 interrupt-controller;
2303 #gpio-cells = <2>;
2304 #interrupt-cells = <2>;
2305 };
2306 };
2307};
2308
2309#include "rk3588s-pinctrl.dtsi"