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git01.mediatek.com / filogic / uboot / 72d61d1c30eb4e01fe3f576ca967efeebd0aacd3 / . / arch / arm / dts / rk3588s.dtsi
blob: 7dbac9ae2e13acd3b342bd545b4862ed3fb0ad77 [file] [log] [blame]
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rk3588-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/power/rk3588-power.h>
10#include <dt-bindings/reset/rockchip,rk3588-cru.h>
11
12/ {
13 compatible = "rockchip,rk3588";
14
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu_l0>;
27 };
28 core1 {
29 cpu = <&cpu_l1>;
30 };
31 core2 {
32 cpu = <&cpu_l2>;
33 };
34 core3 {
35 cpu = <&cpu_l3>;
36 };
37 };
38 cluster1 {
39 core0 {
40 cpu = <&cpu_b0>;
41 };
42 core1 {
43 cpu = <&cpu_b1>;
44 };
45 };
46 cluster2 {
47 core0 {
48 cpu = <&cpu_b2>;
49 };
50 core1 {
51 cpu = <&cpu_b3>;
52 };
53 };
54 };
55
56 cpu_l0: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a55";
59 reg = <0x0>;
60 enable-method = "psci";
61 capacity-dmips-mhz = <530>;
62 clocks = <&scmi_clk SCMI_CLK_CPUL>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]63 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
64 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]65 cpu-idle-states = <&CPU_SLEEP>;
66 i-cache-size = <32768>;
67 i-cache-line-size = <64>;
68 i-cache-sets = <128>;
69 d-cache-size = <32768>;
70 d-cache-line-size = <64>;
71 d-cache-sets = <128>;
72 next-level-cache = <&l2_cache_l0>;
73 dynamic-power-coefficient = <228>;
74 #cooling-cells = <2>;
75 };
76
77 cpu_l1: cpu@100 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a55";
80 reg = <0x100>;
81 enable-method = "psci";
82 capacity-dmips-mhz = <530>;
83 clocks = <&scmi_clk SCMI_CLK_CPUL>;
84 cpu-idle-states = <&CPU_SLEEP>;
85 i-cache-size = <32768>;
86 i-cache-line-size = <64>;
87 i-cache-sets = <128>;
88 d-cache-size = <32768>;
89 d-cache-line-size = <64>;
90 d-cache-sets = <128>;
91 next-level-cache = <&l2_cache_l1>;
92 dynamic-power-coefficient = <228>;
93 #cooling-cells = <2>;
94 };
95
96 cpu_l2: cpu@200 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a55";
99 reg = <0x200>;
100 enable-method = "psci";
101 capacity-dmips-mhz = <530>;
102 clocks = <&scmi_clk SCMI_CLK_CPUL>;
103 cpu-idle-states = <&CPU_SLEEP>;
104 i-cache-size = <32768>;
105 i-cache-line-size = <64>;
106 i-cache-sets = <128>;
107 d-cache-size = <32768>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <128>;
110 next-level-cache = <&l2_cache_l2>;
111 dynamic-power-coefficient = <228>;
112 #cooling-cells = <2>;
113 };
114
115 cpu_l3: cpu@300 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a55";
118 reg = <0x300>;
119 enable-method = "psci";
120 capacity-dmips-mhz = <530>;
121 clocks = <&scmi_clk SCMI_CLK_CPUL>;
122 cpu-idle-states = <&CPU_SLEEP>;
123 i-cache-size = <32768>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <128>;
126 d-cache-size = <32768>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&l2_cache_l3>;
130 dynamic-power-coefficient = <228>;
131 #cooling-cells = <2>;
132 };
133
134 cpu_b0: cpu@400 {
135 device_type = "cpu";
136 compatible = "arm,cortex-a76";
137 reg = <0x400>;
138 enable-method = "psci";
139 capacity-dmips-mhz = <1024>;
140 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]141 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
142 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]143 cpu-idle-states = <&CPU_SLEEP>;
144 i-cache-size = <65536>;
145 i-cache-line-size = <64>;
146 i-cache-sets = <256>;
147 d-cache-size = <65536>;
148 d-cache-line-size = <64>;
149 d-cache-sets = <256>;
150 next-level-cache = <&l2_cache_b0>;
151 dynamic-power-coefficient = <416>;
152 #cooling-cells = <2>;
153 };
154
155 cpu_b1: cpu@500 {
156 device_type = "cpu";
157 compatible = "arm,cortex-a76";
158 reg = <0x500>;
159 enable-method = "psci";
160 capacity-dmips-mhz = <1024>;
161 clocks = <&scmi_clk SCMI_CLK_CPUB01>;
162 cpu-idle-states = <&CPU_SLEEP>;
163 i-cache-size = <65536>;
164 i-cache-line-size = <64>;
165 i-cache-sets = <256>;
166 d-cache-size = <65536>;
167 d-cache-line-size = <64>;
168 d-cache-sets = <256>;
169 next-level-cache = <&l2_cache_b1>;
170 dynamic-power-coefficient = <416>;
171 #cooling-cells = <2>;
172 };
173
174 cpu_b2: cpu@600 {
175 device_type = "cpu";
176 compatible = "arm,cortex-a76";
177 reg = <0x600>;
178 enable-method = "psci";
179 capacity-dmips-mhz = <1024>;
180 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]181 assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
182 assigned-clock-rates = <816000000>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]183 cpu-idle-states = <&CPU_SLEEP>;
184 i-cache-size = <65536>;
185 i-cache-line-size = <64>;
186 i-cache-sets = <256>;
187 d-cache-size = <65536>;
188 d-cache-line-size = <64>;
189 d-cache-sets = <256>;
190 next-level-cache = <&l2_cache_b2>;
191 dynamic-power-coefficient = <416>;
192 #cooling-cells = <2>;
193 };
194
195 cpu_b3: cpu@700 {
196 device_type = "cpu";
197 compatible = "arm,cortex-a76";
198 reg = <0x700>;
199 enable-method = "psci";
200 capacity-dmips-mhz = <1024>;
201 clocks = <&scmi_clk SCMI_CLK_CPUB23>;
202 cpu-idle-states = <&CPU_SLEEP>;
203 i-cache-size = <65536>;
204 i-cache-line-size = <64>;
205 i-cache-sets = <256>;
206 d-cache-size = <65536>;
207 d-cache-line-size = <64>;
208 d-cache-sets = <256>;
209 next-level-cache = <&l2_cache_b3>;
210 dynamic-power-coefficient = <416>;
211 #cooling-cells = <2>;
212 };
213
214 idle-states {
215 entry-method = "psci";
216 CPU_SLEEP: cpu-sleep {
217 compatible = "arm,idle-state";
218 local-timer-stop;
219 arm,psci-suspend-param = <0x0010000>;
220 entry-latency-us = <100>;
221 exit-latency-us = <120>;
222 min-residency-us = <1000>;
223 };
224 };
225
226 l2_cache_l0: l2-cache-l0 {
227 compatible = "cache";
228 cache-size = <131072>;
229 cache-line-size = <64>;
230 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]231 cache-level = <2>;
232 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]233 next-level-cache = <&l3_cache>;
234 };
235
236 l2_cache_l1: l2-cache-l1 {
237 compatible = "cache";
238 cache-size = <131072>;
239 cache-line-size = <64>;
240 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]241 cache-level = <2>;
242 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]243 next-level-cache = <&l3_cache>;
244 };
245
246 l2_cache_l2: l2-cache-l2 {
247 compatible = "cache";
248 cache-size = <131072>;
249 cache-line-size = <64>;
250 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]251 cache-level = <2>;
252 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]253 next-level-cache = <&l3_cache>;
254 };
255
256 l2_cache_l3: l2-cache-l3 {
257 compatible = "cache";
258 cache-size = <131072>;
259 cache-line-size = <64>;
260 cache-sets = <512>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]261 cache-level = <2>;
262 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]263 next-level-cache = <&l3_cache>;
264 };
265
266 l2_cache_b0: l2-cache-b0 {
267 compatible = "cache";
268 cache-size = <524288>;
269 cache-line-size = <64>;
270 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]271 cache-level = <2>;
272 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]273 next-level-cache = <&l3_cache>;
274 };
275
276 l2_cache_b1: l2-cache-b1 {
277 compatible = "cache";
278 cache-size = <524288>;
279 cache-line-size = <64>;
280 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]281 cache-level = <2>;
282 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]283 next-level-cache = <&l3_cache>;
284 };
285
286 l2_cache_b2: l2-cache-b2 {
287 compatible = "cache";
288 cache-size = <524288>;
289 cache-line-size = <64>;
290 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]291 cache-level = <2>;
292 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]293 next-level-cache = <&l3_cache>;
294 };
295
296 l2_cache_b3: l2-cache-b3 {
297 compatible = "cache";
298 cache-size = <524288>;
299 cache-line-size = <64>;
300 cache-sets = <1024>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]301 cache-level = <2>;
302 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]303 next-level-cache = <&l3_cache>;
304 };
305
306 l3_cache: l3-cache {
307 compatible = "cache";
308 cache-size = <3145728>;
309 cache-line-size = <64>;
310 cache-sets = <4096>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]311 cache-level = <3>;
312 cache-unified;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]313 };
314 };
315
316 firmware {
317 optee: optee {
318 compatible = "linaro,optee-tz";
319 method = "smc";
320 };
321
322 scmi: scmi {
323 compatible = "arm,scmi-smc";
324 arm,smc-id = <0x82000010>;
325 shmem = <&scmi_shmem>;
326 #address-cells = <1>;
327 #size-cells = <0>;
328
329 scmi_clk: protocol@14 {
330 reg = <0x14>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]331 #clock-cells = <1>;
332 };
333
334 scmi_reset: protocol@16 {
335 reg = <0x16>;
336 #reset-cells = <1>;
337 };
338 };
339 };
340
341 pmu-a55 {
342 compatible = "arm,cortex-a55-pmu";
343 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
344 };
345
346 pmu-a76 {
347 compatible = "arm,cortex-a76-pmu";
348 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
349 };
350
351 psci {
352 compatible = "arm,psci-1.0";
353 method = "smc";
354 };
355
356 spll: clock-0 {
357 compatible = "fixed-clock";
358 clock-frequency = <702000000>;
359 clock-output-names = "spll";
360 #clock-cells = <0>;
361 };
362
363 timer {
364 compatible = "arm,armv8-timer";
365 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
366 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
367 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
368 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
369 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
370 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
371 };
372
373 xin24m: clock-1 {
374 compatible = "fixed-clock";
375 clock-frequency = <24000000>;
376 clock-output-names = "xin24m";
377 #clock-cells = <0>;
378 };
379
380 xin32k: clock-2 {
381 compatible = "fixed-clock";
382 clock-frequency = <32768>;
383 clock-output-names = "xin32k";
384 #clock-cells = <0>;
385 };
386
387 pmu_sram: sram@10f000 {
388 compatible = "mmio-sram";
389 reg = <0x0 0x0010f000 0x0 0x100>;
390 ranges = <0 0x0 0x0010f000 0x100>;
391 #address-cells = <1>;
392 #size-cells = <1>;
393
394 scmi_shmem: sram@0 {
395 compatible = "arm,scmi-shmem";
396 reg = <0x0 0x100>;
397 };
398 };
399
400 sys_grf: syscon@fd58c000 {
401 compatible = "rockchip,rk3588-sys-grf", "syscon";
402 reg = <0x0 0xfd58c000 0x0 0x1000>;
403 };
404
405 php_grf: syscon@fd5b0000 {
406 compatible = "rockchip,rk3588-php-grf", "syscon";
407 reg = <0x0 0xfd5b0000 0x0 0x1000>;
408 };
409
410 ioc: syscon@fd5f0000 {
411 compatible = "rockchip,rk3588-ioc", "syscon";
412 reg = <0x0 0xfd5f0000 0x0 0x10000>;
413 };
414
415 system_sram1: sram@fd600000 {
416 compatible = "mmio-sram";
417 reg = <0x0 0xfd600000 0x0 0x100000>;
418 ranges = <0x0 0x0 0xfd600000 0x100000>;
419 #address-cells = <1>;
420 #size-cells = <1>;
421 };
422
423 cru: clock-controller@fd7c0000 {
424 compatible = "rockchip,rk3588-cru";
425 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
426 assigned-clocks =
427 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
428 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
429 <&cru ACLK_CENTER_ROOT>,
430 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
431 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
432 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
433 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
434 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
435 <&cru CLK_GPU>;
436 assigned-clock-rates =
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]437 <1100000000>, <786432000>,
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]438 <850000000>, <1188000000>,
439 <702000000>,
440 <400000000>, <500000000>,
441 <800000000>, <100000000>,
442 <400000000>, <100000000>,
443 <200000000>, <500000000>,
444 <375000000>, <150000000>,
445 <200000000>;
446 rockchip,grf = <&php_grf>;
447 #clock-cells = <1>;
448 #reset-cells = <1>;
449 };
450
451 i2c0: i2c@fd880000 {
452 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
453 reg = <0x0 0xfd880000 0x0 0x1000>;
454 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
455 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
456 clock-names = "i2c", "pclk";
457 pinctrl-0 = <&i2c0m0_xfer>;
458 pinctrl-names = "default";
459 #address-cells = <1>;
460 #size-cells = <0>;
461 status = "disabled";
462 };
463
464 uart0: serial@fd890000 {
465 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
466 reg = <0x0 0xfd890000 0x0 0x100>;
467 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
468 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
469 clock-names = "baudclk", "apb_pclk";
470 dmas = <&dmac0 6>, <&dmac0 7>;
471 dma-names = "tx", "rx";
472 pinctrl-0 = <&uart0m1_xfer>;
473 pinctrl-names = "default";
474 reg-shift = <2>;
475 reg-io-width = <4>;
476 status = "disabled";
477 };
478
479 pwm0: pwm@fd8b0000 {
480 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
481 reg = <0x0 0xfd8b0000 0x0 0x10>;
482 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
483 clock-names = "pwm", "pclk";
484 pinctrl-0 = <&pwm0m0_pins>;
485 pinctrl-names = "default";
486 #pwm-cells = <3>;
487 status = "disabled";
488 };
489
490 pwm1: pwm@fd8b0010 {
491 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
492 reg = <0x0 0xfd8b0010 0x0 0x10>;
493 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
494 clock-names = "pwm", "pclk";
495 pinctrl-0 = <&pwm1m0_pins>;
496 pinctrl-names = "default";
497 #pwm-cells = <3>;
498 status = "disabled";
499 };
500
501 pwm2: pwm@fd8b0020 {
502 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
503 reg = <0x0 0xfd8b0020 0x0 0x10>;
504 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
505 clock-names = "pwm", "pclk";
506 pinctrl-0 = <&pwm2m0_pins>;
507 pinctrl-names = "default";
508 #pwm-cells = <3>;
509 status = "disabled";
510 };
511
512 pwm3: pwm@fd8b0030 {
513 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
514 reg = <0x0 0xfd8b0030 0x0 0x10>;
515 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
516 clock-names = "pwm", "pclk";
517 pinctrl-0 = <&pwm3m0_pins>;
518 pinctrl-names = "default";
519 #pwm-cells = <3>;
520 status = "disabled";
521 };
522
523 pmu: power-management@fd8d8000 {
524 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
525 reg = <0x0 0xfd8d8000 0x0 0x400>;
526
527 power: power-controller {
528 compatible = "rockchip,rk3588-power-controller";
529 #address-cells = <1>;
530 #power-domain-cells = <1>;
531 #size-cells = <0>;
532 status = "okay";
533
534 /* These power domains are grouped by VD_NPU */
535 power-domain@RK3588_PD_NPU {
536 reg = <RK3588_PD_NPU>;
537 #power-domain-cells = <0>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540
541 power-domain@RK3588_PD_NPUTOP {
542 reg = <RK3588_PD_NPUTOP>;
543 clocks = <&cru HCLK_NPU_ROOT>,
544 <&cru PCLK_NPU_ROOT>,
545 <&cru CLK_NPU_DSU0>,
546 <&cru HCLK_NPU_CM0_ROOT>;
547 pm_qos = <&qos_npu0_mwr>,
548 <&qos_npu0_mro>,
549 <&qos_mcu_npu>;
550 #power-domain-cells = <0>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553
554 power-domain@RK3588_PD_NPU1 {
555 reg = <RK3588_PD_NPU1>;
556 clocks = <&cru HCLK_NPU_ROOT>,
557 <&cru PCLK_NPU_ROOT>,
558 <&cru CLK_NPU_DSU0>;
559 pm_qos = <&qos_npu1>;
560 #power-domain-cells = <0>;
561 };
562 power-domain@RK3588_PD_NPU2 {
563 reg = <RK3588_PD_NPU2>;
564 clocks = <&cru HCLK_NPU_ROOT>,
565 <&cru PCLK_NPU_ROOT>,
566 <&cru CLK_NPU_DSU0>;
567 pm_qos = <&qos_npu2>;
568 #power-domain-cells = <0>;
569 };
570 };
571 };
572 /* These power domains are grouped by VD_GPU */
573 power-domain@RK3588_PD_GPU {
574 reg = <RK3588_PD_GPU>;
575 clocks = <&cru CLK_GPU>,
576 <&cru CLK_GPU_COREGROUP>,
577 <&cru CLK_GPU_STACKS>;
578 pm_qos = <&qos_gpu_m0>,
579 <&qos_gpu_m1>,
580 <&qos_gpu_m2>,
581 <&qos_gpu_m3>;
582 #power-domain-cells = <0>;
583 };
584 /* These power domains are grouped by VD_VCODEC */
585 power-domain@RK3588_PD_VCODEC {
586 reg = <RK3588_PD_VCODEC>;
587 #address-cells = <1>;
588 #size-cells = <0>;
589 #power-domain-cells = <0>;
590
591 power-domain@RK3588_PD_RKVDEC0 {
592 reg = <RK3588_PD_RKVDEC0>;
593 clocks = <&cru HCLK_RKVDEC0>,
594 <&cru HCLK_VDPU_ROOT>,
595 <&cru ACLK_VDPU_ROOT>,
596 <&cru ACLK_RKVDEC0>,
597 <&cru ACLK_RKVDEC_CCU>;
598 pm_qos = <&qos_rkvdec0>;
599 #power-domain-cells = <0>;
600 };
601 power-domain@RK3588_PD_RKVDEC1 {
602 reg = <RK3588_PD_RKVDEC1>;
603 clocks = <&cru HCLK_RKVDEC1>,
604 <&cru HCLK_VDPU_ROOT>,
605 <&cru ACLK_VDPU_ROOT>,
606 <&cru ACLK_RKVDEC1>;
607 pm_qos = <&qos_rkvdec1>;
608 #power-domain-cells = <0>;
609 };
610 power-domain@RK3588_PD_VENC0 {
611 reg = <RK3588_PD_VENC0>;
612 clocks = <&cru HCLK_RKVENC0>,
613 <&cru ACLK_RKVENC0>;
614 pm_qos = <&qos_rkvenc0_m0ro>,
615 <&qos_rkvenc0_m1ro>,
616 <&qos_rkvenc0_m2wo>;
617 #address-cells = <1>;
618 #size-cells = <0>;
619 #power-domain-cells = <0>;
620
621 power-domain@RK3588_PD_VENC1 {
622 reg = <RK3588_PD_VENC1>;
623 clocks = <&cru HCLK_RKVENC1>,
624 <&cru HCLK_RKVENC0>,
625 <&cru ACLK_RKVENC0>,
626 <&cru ACLK_RKVENC1>;
627 pm_qos = <&qos_rkvenc1_m0ro>,
628 <&qos_rkvenc1_m1ro>,
629 <&qos_rkvenc1_m2wo>;
630 #power-domain-cells = <0>;
631 };
632 };
633 };
634 /* These power domains are grouped by VD_LOGIC */
635 power-domain@RK3588_PD_VDPU {
636 reg = <RK3588_PD_VDPU>;
637 clocks = <&cru HCLK_VDPU_ROOT>,
638 <&cru ACLK_VDPU_LOW_ROOT>,
639 <&cru ACLK_VDPU_ROOT>,
640 <&cru ACLK_JPEG_DECODER_ROOT>,
641 <&cru ACLK_IEP2P0>,
642 <&cru HCLK_IEP2P0>,
643 <&cru ACLK_JPEG_ENCODER0>,
644 <&cru HCLK_JPEG_ENCODER0>,
645 <&cru ACLK_JPEG_ENCODER1>,
646 <&cru HCLK_JPEG_ENCODER1>,
647 <&cru ACLK_JPEG_ENCODER2>,
648 <&cru HCLK_JPEG_ENCODER2>,
649 <&cru ACLK_JPEG_ENCODER3>,
650 <&cru HCLK_JPEG_ENCODER3>,
651 <&cru ACLK_JPEG_DECODER>,
652 <&cru HCLK_JPEG_DECODER>,
653 <&cru ACLK_RGA2>,
654 <&cru HCLK_RGA2>;
655 pm_qos = <&qos_iep>,
656 <&qos_jpeg_dec>,
657 <&qos_jpeg_enc0>,
658 <&qos_jpeg_enc1>,
659 <&qos_jpeg_enc2>,
660 <&qos_jpeg_enc3>,
661 <&qos_rga2_mro>,
662 <&qos_rga2_mwo>;
663 #address-cells = <1>;
664 #size-cells = <0>;
665 #power-domain-cells = <0>;
666
667
668 power-domain@RK3588_PD_AV1 {
669 reg = <RK3588_PD_AV1>;
670 clocks = <&cru PCLK_AV1>,
671 <&cru ACLK_AV1>,
672 <&cru HCLK_VDPU_ROOT>;
673 pm_qos = <&qos_av1>;
674 #power-domain-cells = <0>;
675 };
676 power-domain@RK3588_PD_RKVDEC0 {
677 reg = <RK3588_PD_RKVDEC0>;
678 clocks = <&cru HCLK_RKVDEC0>,
679 <&cru HCLK_VDPU_ROOT>,
680 <&cru ACLK_VDPU_ROOT>,
681 <&cru ACLK_RKVDEC0>;
682 pm_qos = <&qos_rkvdec0>;
683 #power-domain-cells = <0>;
684 };
685 power-domain@RK3588_PD_RKVDEC1 {
686 reg = <RK3588_PD_RKVDEC1>;
687 clocks = <&cru HCLK_RKVDEC1>,
688 <&cru HCLK_VDPU_ROOT>,
689 <&cru ACLK_VDPU_ROOT>;
690 pm_qos = <&qos_rkvdec1>;
691 #power-domain-cells = <0>;
692 };
693 power-domain@RK3588_PD_RGA30 {
694 reg = <RK3588_PD_RGA30>;
695 clocks = <&cru ACLK_RGA3_0>,
696 <&cru HCLK_RGA3_0>;
697 pm_qos = <&qos_rga3_0>;
698 #power-domain-cells = <0>;
699 };
700 };
701 power-domain@RK3588_PD_VOP {
702 reg = <RK3588_PD_VOP>;
703 clocks = <&cru PCLK_VOP_ROOT>,
704 <&cru HCLK_VOP_ROOT>,
705 <&cru ACLK_VOP>;
706 pm_qos = <&qos_vop_m0>,
707 <&qos_vop_m1>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 #power-domain-cells = <0>;
711
712 power-domain@RK3588_PD_VO0 {
713 reg = <RK3588_PD_VO0>;
714 clocks = <&cru PCLK_VO0_ROOT>,
715 <&cru PCLK_VO0_S_ROOT>,
716 <&cru HCLK_VO0_S_ROOT>,
717 <&cru ACLK_VO0_ROOT>,
718 <&cru HCLK_HDCP0>,
719 <&cru ACLK_HDCP0>,
720 <&cru HCLK_VOP_ROOT>;
721 pm_qos = <&qos_hdcp0>;
722 #power-domain-cells = <0>;
723 };
724 };
725 power-domain@RK3588_PD_VO1 {
726 reg = <RK3588_PD_VO1>;
727 clocks = <&cru PCLK_VO1_ROOT>,
728 <&cru PCLK_VO1_S_ROOT>,
729 <&cru HCLK_VO1_S_ROOT>,
730 <&cru HCLK_HDCP1>,
731 <&cru ACLK_HDCP1>,
732 <&cru ACLK_HDMIRX_ROOT>,
733 <&cru HCLK_VO1USB_TOP_ROOT>;
734 pm_qos = <&qos_hdcp1>,
735 <&qos_hdmirx>;
736 #power-domain-cells = <0>;
737 };
738 power-domain@RK3588_PD_VI {
739 reg = <RK3588_PD_VI>;
740 clocks = <&cru HCLK_VI_ROOT>,
741 <&cru PCLK_VI_ROOT>,
742 <&cru HCLK_ISP0>,
743 <&cru ACLK_ISP0>,
744 <&cru HCLK_VICAP>,
745 <&cru ACLK_VICAP>;
746 pm_qos = <&qos_isp0_mro>,
747 <&qos_isp0_mwo>,
748 <&qos_vicap_m0>,
749 <&qos_vicap_m1>;
750 #address-cells = <1>;
751 #size-cells = <0>;
752 #power-domain-cells = <0>;
753
754 power-domain@RK3588_PD_ISP1 {
755 reg = <RK3588_PD_ISP1>;
756 clocks = <&cru HCLK_ISP1>,
757 <&cru ACLK_ISP1>,
758 <&cru HCLK_VI_ROOT>,
759 <&cru PCLK_VI_ROOT>;
760 pm_qos = <&qos_isp1_mwo>,
761 <&qos_isp1_mro>;
762 #power-domain-cells = <0>;
763 };
764 power-domain@RK3588_PD_FEC {
765 reg = <RK3588_PD_FEC>;
766 clocks = <&cru HCLK_FISHEYE0>,
767 <&cru ACLK_FISHEYE0>,
768 <&cru HCLK_FISHEYE1>,
769 <&cru ACLK_FISHEYE1>,
770 <&cru PCLK_VI_ROOT>;
771 pm_qos = <&qos_fisheye0>,
772 <&qos_fisheye1>;
773 #power-domain-cells = <0>;
774 };
775 };
776 power-domain@RK3588_PD_RGA31 {
777 reg = <RK3588_PD_RGA31>;
778 clocks = <&cru HCLK_RGA3_1>,
779 <&cru ACLK_RGA3_1>;
780 pm_qos = <&qos_rga3_1>;
781 #power-domain-cells = <0>;
782 };
783 power-domain@RK3588_PD_USB {
784 reg = <RK3588_PD_USB>;
785 clocks = <&cru PCLK_PHP_ROOT>,
786 <&cru ACLK_USB_ROOT>,
787 <&cru HCLK_USB_ROOT>,
788 <&cru HCLK_HOST0>,
789 <&cru HCLK_HOST_ARB0>,
790 <&cru HCLK_HOST1>,
791 <&cru HCLK_HOST_ARB1>;
792 pm_qos = <&qos_usb3_0>,
793 <&qos_usb3_1>,
794 <&qos_usb2host_0>,
795 <&qos_usb2host_1>;
796 #power-domain-cells = <0>;
797 };
798 power-domain@RK3588_PD_GMAC {
799 reg = <RK3588_PD_GMAC>;
800 clocks = <&cru PCLK_PHP_ROOT>,
801 <&cru ACLK_PCIE_ROOT>,
802 <&cru ACLK_PHP_ROOT>;
803 #power-domain-cells = <0>;
804 };
805 power-domain@RK3588_PD_PCIE {
806 reg = <RK3588_PD_PCIE>;
807 clocks = <&cru PCLK_PHP_ROOT>,
808 <&cru ACLK_PCIE_ROOT>,
809 <&cru ACLK_PHP_ROOT>;
810 #power-domain-cells = <0>;
811 };
812 power-domain@RK3588_PD_SDIO {
813 reg = <RK3588_PD_SDIO>;
814 clocks = <&cru HCLK_SDIO>,
815 <&cru HCLK_NVM_ROOT>;
816 pm_qos = <&qos_sdio>;
817 #power-domain-cells = <0>;
818 };
819 power-domain@RK3588_PD_AUDIO {
820 reg = <RK3588_PD_AUDIO>;
821 clocks = <&cru HCLK_AUDIO_ROOT>,
822 <&cru PCLK_AUDIO_ROOT>;
823 #power-domain-cells = <0>;
824 };
825 power-domain@RK3588_PD_SDMMC {
826 reg = <RK3588_PD_SDMMC>;
827 pm_qos = <&qos_sdmmc>;
828 #power-domain-cells = <0>;
829 };
830 };
831 };
832
833 qos_gpu_m0: qos@fdf35000 {
834 compatible = "rockchip,rk3588-qos", "syscon";
835 reg = <0x0 0xfdf35000 0x0 0x20>;
836 };
837
838 qos_gpu_m1: qos@fdf35200 {
839 compatible = "rockchip,rk3588-qos", "syscon";
840 reg = <0x0 0xfdf35200 0x0 0x20>;
841 };
842
843 qos_gpu_m2: qos@fdf35400 {
844 compatible = "rockchip,rk3588-qos", "syscon";
845 reg = <0x0 0xfdf35400 0x0 0x20>;
846 };
847
848 qos_gpu_m3: qos@fdf35600 {
849 compatible = "rockchip,rk3588-qos", "syscon";
850 reg = <0x0 0xfdf35600 0x0 0x20>;
851 };
852
853 qos_rga3_1: qos@fdf36000 {
854 compatible = "rockchip,rk3588-qos", "syscon";
855 reg = <0x0 0xfdf36000 0x0 0x20>;
856 };
857
858 qos_sdio: qos@fdf39000 {
859 compatible = "rockchip,rk3588-qos", "syscon";
860 reg = <0x0 0xfdf39000 0x0 0x20>;
861 };
862
863 qos_sdmmc: qos@fdf3d800 {
864 compatible = "rockchip,rk3588-qos", "syscon";
865 reg = <0x0 0xfdf3d800 0x0 0x20>;
866 };
867
868 qos_usb3_1: qos@fdf3e000 {
869 compatible = "rockchip,rk3588-qos", "syscon";
870 reg = <0x0 0xfdf3e000 0x0 0x20>;
871 };
872
873 qos_usb3_0: qos@fdf3e200 {
874 compatible = "rockchip,rk3588-qos", "syscon";
875 reg = <0x0 0xfdf3e200 0x0 0x20>;
876 };
877
878 qos_usb2host_0: qos@fdf3e400 {
879 compatible = "rockchip,rk3588-qos", "syscon";
880 reg = <0x0 0xfdf3e400 0x0 0x20>;
881 };
882
883 qos_usb2host_1: qos@fdf3e600 {
884 compatible = "rockchip,rk3588-qos", "syscon";
885 reg = <0x0 0xfdf3e600 0x0 0x20>;
886 };
887
888 qos_fisheye0: qos@fdf40000 {
889 compatible = "rockchip,rk3588-qos", "syscon";
890 reg = <0x0 0xfdf40000 0x0 0x20>;
891 };
892
893 qos_fisheye1: qos@fdf40200 {
894 compatible = "rockchip,rk3588-qos", "syscon";
895 reg = <0x0 0xfdf40200 0x0 0x20>;
896 };
897
898 qos_isp0_mro: qos@fdf40400 {
899 compatible = "rockchip,rk3588-qos", "syscon";
900 reg = <0x0 0xfdf40400 0x0 0x20>;
901 };
902
903 qos_isp0_mwo: qos@fdf40500 {
904 compatible = "rockchip,rk3588-qos", "syscon";
905 reg = <0x0 0xfdf40500 0x0 0x20>;
906 };
907
908 qos_vicap_m0: qos@fdf40600 {
909 compatible = "rockchip,rk3588-qos", "syscon";
910 reg = <0x0 0xfdf40600 0x0 0x20>;
911 };
912
913 qos_vicap_m1: qos@fdf40800 {
914 compatible = "rockchip,rk3588-qos", "syscon";
915 reg = <0x0 0xfdf40800 0x0 0x20>;
916 };
917
918 qos_isp1_mwo: qos@fdf41000 {
919 compatible = "rockchip,rk3588-qos", "syscon";
920 reg = <0x0 0xfdf41000 0x0 0x20>;
921 };
922
923 qos_isp1_mro: qos@fdf41100 {
924 compatible = "rockchip,rk3588-qos", "syscon";
925 reg = <0x0 0xfdf41100 0x0 0x20>;
926 };
927
928 qos_rkvenc0_m0ro: qos@fdf60000 {
929 compatible = "rockchip,rk3588-qos", "syscon";
930 reg = <0x0 0xfdf60000 0x0 0x20>;
931 };
932
933 qos_rkvenc0_m1ro: qos@fdf60200 {
934 compatible = "rockchip,rk3588-qos", "syscon";
935 reg = <0x0 0xfdf60200 0x0 0x20>;
936 };
937
938 qos_rkvenc0_m2wo: qos@fdf60400 {
939 compatible = "rockchip,rk3588-qos", "syscon";
940 reg = <0x0 0xfdf60400 0x0 0x20>;
941 };
942
943 qos_rkvenc1_m0ro: qos@fdf61000 {
944 compatible = "rockchip,rk3588-qos", "syscon";
945 reg = <0x0 0xfdf61000 0x0 0x20>;
946 };
947
948 qos_rkvenc1_m1ro: qos@fdf61200 {
949 compatible = "rockchip,rk3588-qos", "syscon";
950 reg = <0x0 0xfdf61200 0x0 0x20>;
951 };
952
953 qos_rkvenc1_m2wo: qos@fdf61400 {
954 compatible = "rockchip,rk3588-qos", "syscon";
955 reg = <0x0 0xfdf61400 0x0 0x20>;
956 };
957
958 qos_rkvdec0: qos@fdf62000 {
959 compatible = "rockchip,rk3588-qos", "syscon";
960 reg = <0x0 0xfdf62000 0x0 0x20>;
961 };
962
963 qos_rkvdec1: qos@fdf63000 {
964 compatible = "rockchip,rk3588-qos", "syscon";
965 reg = <0x0 0xfdf63000 0x0 0x20>;
966 };
967
968 qos_av1: qos@fdf64000 {
969 compatible = "rockchip,rk3588-qos", "syscon";
970 reg = <0x0 0xfdf64000 0x0 0x20>;
971 };
972
973 qos_iep: qos@fdf66000 {
974 compatible = "rockchip,rk3588-qos", "syscon";
975 reg = <0x0 0xfdf66000 0x0 0x20>;
976 };
977
978 qos_jpeg_dec: qos@fdf66200 {
979 compatible = "rockchip,rk3588-qos", "syscon";
980 reg = <0x0 0xfdf66200 0x0 0x20>;
981 };
982
983 qos_jpeg_enc0: qos@fdf66400 {
984 compatible = "rockchip,rk3588-qos", "syscon";
985 reg = <0x0 0xfdf66400 0x0 0x20>;
986 };
987
988 qos_jpeg_enc1: qos@fdf66600 {
989 compatible = "rockchip,rk3588-qos", "syscon";
990 reg = <0x0 0xfdf66600 0x0 0x20>;
991 };
992
993 qos_jpeg_enc2: qos@fdf66800 {
994 compatible = "rockchip,rk3588-qos", "syscon";
995 reg = <0x0 0xfdf66800 0x0 0x20>;
996 };
997
998 qos_jpeg_enc3: qos@fdf66a00 {
999 compatible = "rockchip,rk3588-qos", "syscon";
1000 reg = <0x0 0xfdf66a00 0x0 0x20>;
1001 };
1002
1003 qos_rga2_mro: qos@fdf66c00 {
1004 compatible = "rockchip,rk3588-qos", "syscon";
1005 reg = <0x0 0xfdf66c00 0x0 0x20>;
1006 };
1007
1008 qos_rga2_mwo: qos@fdf66e00 {
1009 compatible = "rockchip,rk3588-qos", "syscon";
1010 reg = <0x0 0xfdf66e00 0x0 0x20>;
1011 };
1012
1013 qos_rga3_0: qos@fdf67000 {
1014 compatible = "rockchip,rk3588-qos", "syscon";
1015 reg = <0x0 0xfdf67000 0x0 0x20>;
1016 };
1017
1018 qos_vdpu: qos@fdf67200 {
1019 compatible = "rockchip,rk3588-qos", "syscon";
1020 reg = <0x0 0xfdf67200 0x0 0x20>;
1021 };
1022
1023 qos_npu1: qos@fdf70000 {
1024 compatible = "rockchip,rk3588-qos", "syscon";
1025 reg = <0x0 0xfdf70000 0x0 0x20>;
1026 };
1027
1028 qos_npu2: qos@fdf71000 {
1029 compatible = "rockchip,rk3588-qos", "syscon";
1030 reg = <0x0 0xfdf71000 0x0 0x20>;
1031 };
1032
1033 qos_npu0_mwr: qos@fdf72000 {
1034 compatible = "rockchip,rk3588-qos", "syscon";
1035 reg = <0x0 0xfdf72000 0x0 0x20>;
1036 };
1037
1038 qos_npu0_mro: qos@fdf72200 {
1039 compatible = "rockchip,rk3588-qos", "syscon";
1040 reg = <0x0 0xfdf72200 0x0 0x20>;
1041 };
1042
1043 qos_mcu_npu: qos@fdf72400 {
1044 compatible = "rockchip,rk3588-qos", "syscon";
1045 reg = <0x0 0xfdf72400 0x0 0x20>;
1046 };
1047
1048 qos_hdcp0: qos@fdf80000 {
1049 compatible = "rockchip,rk3588-qos", "syscon";
1050 reg = <0x0 0xfdf80000 0x0 0x20>;
1051 };
1052
1053 qos_hdcp1: qos@fdf81000 {
1054 compatible = "rockchip,rk3588-qos", "syscon";
1055 reg = <0x0 0xfdf81000 0x0 0x20>;
1056 };
1057
1058 qos_hdmirx: qos@fdf81200 {
1059 compatible = "rockchip,rk3588-qos", "syscon";
1060 reg = <0x0 0xfdf81200 0x0 0x20>;
1061 };
1062
1063 qos_vop_m0: qos@fdf82000 {
1064 compatible = "rockchip,rk3588-qos", "syscon";
1065 reg = <0x0 0xfdf82000 0x0 0x20>;
1066 };
1067
1068 qos_vop_m1: qos@fdf82200 {
1069 compatible = "rockchip,rk3588-qos", "syscon";
1070 reg = <0x0 0xfdf82200 0x0 0x20>;
1071 };
1072
1073 gmac1: ethernet@fe1c0000 {
1074 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
1075 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1076 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
1077 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
1078 interrupt-names = "macirq", "eth_wake_irq";
1079 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1080 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1081 <&cru CLK_GMAC1_PTP_REF>;
1082 clock-names = "stmmaceth", "clk_mac_ref",
1083 "pclk_mac", "aclk_mac",
1084 "ptp_ref";
1085 power-domains = <&power RK3588_PD_GMAC>;
1086 resets = <&cru SRST_A_GMAC1>;
1087 reset-names = "stmmaceth";
1088 rockchip,grf = <&sys_grf>;
1089 rockchip,php-grf = <&php_grf>;
1090 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1091 snps,mixed-burst;
1092 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1093 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1094 snps,tso;
1095 status = "disabled";
1096
1097 mdio1: mdio {
1098 compatible = "snps,dwmac-mdio";
1099 #address-cells = <0x1>;
1100 #size-cells = <0x0>;
1101 };
1102
1103 gmac1_stmmac_axi_setup: stmmac-axi-config {
1104 snps,blen = <0 0 0 0 16 8 4>;
1105 snps,wr_osr_lmt = <4>;
1106 snps,rd_osr_lmt = <8>;
1107 };
1108
1109 gmac1_mtl_rx_setup: rx-queues-config {
1110 snps,rx-queues-to-use = <2>;
1111 queue0 {};
1112 queue1 {};
1113 };
1114
1115 gmac1_mtl_tx_setup: tx-queues-config {
1116 snps,tx-queues-to-use = <2>;
1117 queue0 {};
1118 queue1 {};
1119 };
1120 };
1121
Jonas Karlmanfc805c22023-04-17 19:07:21 +0000[diff] [blame]1122 sdmmc: mmc@fe2c0000 {
1123 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
1124 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1125 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
1126 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
1127 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1128 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1129 fifo-depth = <0x100>;
1130 max-frequency = <200000000>;
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1133 power-domains = <&power RK3588_PD_SDMMC>;
1134 status = "disabled";
1135 };
1136
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1137 sdhci: mmc@fe2e0000 {
1138 compatible = "rockchip,rk3588-dwcmshc";
1139 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1140 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1141 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1142 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1143 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1144 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1145 <&cru TMCLK_EMMC>;
1146 clock-names = "core", "bus", "axi", "block", "timer";
1147 max-frequency = <200000000>;
1148 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1149 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1150 <&cru SRST_T_EMMC>;
1151 reset-names = "core", "bus", "axi", "block", "timer";
1152 status = "disabled";
1153 };
1154
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1155 i2s0_8ch: i2s@fe470000 {
1156 compatible = "rockchip,rk3588-i2s-tdm";
1157 reg = <0x0 0xfe470000 0x0 0x1000>;
1158 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
1159 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1160 clock-names = "mclk_tx", "mclk_rx", "hclk";
1161 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1162 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1163 dmas = <&dmac0 0>, <&dmac0 1>;
1164 dma-names = "tx", "rx";
1165 power-domains = <&power RK3588_PD_AUDIO>;
1166 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1167 reset-names = "tx-m", "rx-m";
1168 rockchip,trcm-sync-tx-only;
1169 pinctrl-names = "default";
1170 pinctrl-0 = <&i2s0_lrck
1171 &i2s0_sclk
1172 &i2s0_sdi0
1173 &i2s0_sdi1
1174 &i2s0_sdi2
1175 &i2s0_sdi3
1176 &i2s0_sdo0
1177 &i2s0_sdo1
1178 &i2s0_sdo2
1179 &i2s0_sdo3>;
1180 #sound-dai-cells = <0>;
1181 status = "disabled";
1182 };
1183
1184 i2s1_8ch: i2s@fe480000 {
1185 compatible = "rockchip,rk3588-i2s-tdm";
1186 reg = <0x0 0xfe480000 0x0 0x1000>;
1187 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
1188 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1189 clock-names = "mclk_tx", "mclk_rx", "hclk";
1190 dmas = <&dmac0 2>, <&dmac0 3>;
1191 dma-names = "tx", "rx";
1192 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1193 reset-names = "tx-m", "rx-m";
1194 rockchip,trcm-sync-tx-only;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&i2s1m0_lrck
1197 &i2s1m0_sclk
1198 &i2s1m0_sdi0
1199 &i2s1m0_sdi1
1200 &i2s1m0_sdi2
1201 &i2s1m0_sdi3
1202 &i2s1m0_sdo0
1203 &i2s1m0_sdo1
1204 &i2s1m0_sdo2
1205 &i2s1m0_sdo3>;
1206 #sound-dai-cells = <0>;
1207 status = "disabled";
1208 };
1209
1210 i2s2_2ch: i2s@fe490000 {
1211 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1212 reg = <0x0 0xfe490000 0x0 0x1000>;
1213 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
1214 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1215 clock-names = "i2s_clk", "i2s_hclk";
1216 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1217 assigned-clock-parents = <&cru PLL_AUPLL>;
1218 dmas = <&dmac1 0>, <&dmac1 1>;
1219 dma-names = "tx", "rx";
1220 power-domains = <&power RK3588_PD_AUDIO>;
1221 rockchip,trcm-sync-tx-only;
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&i2s2m1_lrck
1224 &i2s2m1_sclk
1225 &i2s2m1_sdi
1226 &i2s2m1_sdo>;
1227 #sound-dai-cells = <0>;
1228 status = "disabled";
1229 };
1230
1231 i2s3_2ch: i2s@fe4a0000 {
1232 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
1233 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1234 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
1235 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1236 clock-names = "i2s_clk", "i2s_hclk";
1237 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1238 assigned-clock-parents = <&cru PLL_AUPLL>;
1239 dmas = <&dmac1 2>, <&dmac1 3>;
1240 dma-names = "tx", "rx";
1241 power-domains = <&power RK3588_PD_AUDIO>;
1242 rockchip,trcm-sync-tx-only;
1243 pinctrl-names = "default";
1244 pinctrl-0 = <&i2s3_lrck
1245 &i2s3_sclk
1246 &i2s3_sdi
1247 &i2s3_sdo>;
1248 #sound-dai-cells = <0>;
1249 status = "disabled";
1250 };
1251
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1252 gic: interrupt-controller@fe600000 {
1253 compatible = "arm,gic-v3";
1254 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1255 <0x0 0xfe680000 0 0x100000>; /* GICR */
1256 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
1257 interrupt-controller;
1258 mbi-alias = <0x0 0xfe610000>;
1259 mbi-ranges = <424 56>;
1260 msi-controller;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1261 ranges;
1262 #address-cells = <2>;
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1263 #interrupt-cells = <4>;
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1264 #size-cells = <2>;
1265
1266 its0: msi-controller@fe640000 {
1267 compatible = "arm,gic-v3-its";
1268 reg = <0x0 0xfe640000 0x0 0x20000>;
1269 msi-controller;
1270 #msi-cells = <1>;
1271 };
1272
1273 its1: msi-controller@fe660000 {
1274 compatible = "arm,gic-v3-its";
1275 reg = <0x0 0xfe660000 0x0 0x20000>;
1276 msi-controller;
1277 #msi-cells = <1>;
1278 };
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1279
1280 ppi-partitions {
1281 ppi_partition0: interrupt-partition-0 {
1282 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
1283 };
1284
1285 ppi_partition1: interrupt-partition-1 {
1286 affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
1287 };
1288 };
1289 };
1290
1291 dmac0: dma-controller@fea10000 {
1292 compatible = "arm,pl330", "arm,primecell";
1293 reg = <0x0 0xfea10000 0x0 0x4000>;
1294 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
1295 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
1296 arm,pl330-periph-burst;
1297 clocks = <&cru ACLK_DMAC0>;
1298 clock-names = "apb_pclk";
1299 #dma-cells = <1>;
1300 };
1301
1302 dmac1: dma-controller@fea30000 {
1303 compatible = "arm,pl330", "arm,primecell";
1304 reg = <0x0 0xfea30000 0x0 0x4000>;
1305 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
1306 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
1307 arm,pl330-periph-burst;
1308 clocks = <&cru ACLK_DMAC1>;
1309 clock-names = "apb_pclk";
1310 #dma-cells = <1>;
1311 };
1312
1313 i2c1: i2c@fea90000 {
1314 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1315 reg = <0x0 0xfea90000 0x0 0x1000>;
1316 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1317 clock-names = "i2c", "pclk";
1318 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
1319 pinctrl-0 = <&i2c1m0_xfer>;
1320 pinctrl-names = "default";
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1323 status = "disabled";
1324 };
1325
1326 i2c2: i2c@feaa0000 {
1327 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1328 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1329 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1330 clock-names = "i2c", "pclk";
1331 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
1332 pinctrl-0 = <&i2c2m0_xfer>;
1333 pinctrl-names = "default";
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 status = "disabled";
1337 };
1338
1339 i2c3: i2c@feab0000 {
1340 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1341 reg = <0x0 0xfeab0000 0x0 0x1000>;
1342 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1343 clock-names = "i2c", "pclk";
1344 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
1345 pinctrl-0 = <&i2c3m0_xfer>;
1346 pinctrl-names = "default";
1347 #address-cells = <1>;
1348 #size-cells = <0>;
1349 status = "disabled";
1350 };
1351
1352 i2c4: i2c@feac0000 {
1353 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1354 reg = <0x0 0xfeac0000 0x0 0x1000>;
1355 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1356 clock-names = "i2c", "pclk";
1357 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
1358 pinctrl-0 = <&i2c4m0_xfer>;
1359 pinctrl-names = "default";
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1362 status = "disabled";
1363 };
1364
1365 i2c5: i2c@fead0000 {
1366 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1367 reg = <0x0 0xfead0000 0x0 0x1000>;
1368 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1369 clock-names = "i2c", "pclk";
1370 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
1371 pinctrl-0 = <&i2c5m0_xfer>;
1372 pinctrl-names = "default";
1373 #address-cells = <1>;
1374 #size-cells = <0>;
1375 status = "disabled";
1376 };
1377
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1378 timer0: timer@feae0000 {
1379 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
1380 reg = <0x0 0xfeae0000 0x0 0x20>;
1381 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
1382 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1383 clock-names = "pclk", "timer";
1384 };
1385
1386 wdt: watchdog@feaf0000 {
1387 compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
1388 reg = <0x0 0xfeaf0000 0x0 0x100>;
1389 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1390 clock-names = "tclk", "pclk";
1391 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
1392 };
1393
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1394 spi0: spi@feb00000 {
1395 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1396 reg = <0x0 0xfeb00000 0x0 0x1000>;
1397 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
1398 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1399 clock-names = "spiclk", "apb_pclk";
1400 dmas = <&dmac0 14>, <&dmac0 15>;
1401 dma-names = "tx", "rx";
1402 num-cs = <2>;
1403 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1404 pinctrl-names = "default";
1405 #address-cells = <1>;
1406 #size-cells = <0>;
1407 status = "disabled";
1408 };
1409
1410 spi1: spi@feb10000 {
1411 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1412 reg = <0x0 0xfeb10000 0x0 0x1000>;
1413 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
1414 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1415 clock-names = "spiclk", "apb_pclk";
1416 dmas = <&dmac0 16>, <&dmac0 17>;
1417 dma-names = "tx", "rx";
1418 num-cs = <2>;
1419 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1420 pinctrl-names = "default";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 status = "disabled";
1424 };
1425
1426 spi2: spi@feb20000 {
1427 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1428 reg = <0x0 0xfeb20000 0x0 0x1000>;
1429 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
1430 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1431 clock-names = "spiclk", "apb_pclk";
1432 dmas = <&dmac1 15>, <&dmac1 16>;
1433 dma-names = "tx", "rx";
1434 num-cs = <2>;
1435 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
1436 pinctrl-names = "default";
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1439 status = "disabled";
1440 };
1441
1442 spi3: spi@feb30000 {
1443 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1444 reg = <0x0 0xfeb30000 0x0 0x1000>;
1445 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
1446 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1447 clock-names = "spiclk", "apb_pclk";
1448 dmas = <&dmac1 17>, <&dmac1 18>;
1449 dma-names = "tx", "rx";
1450 num-cs = <2>;
1451 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1452 pinctrl-names = "default";
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455 status = "disabled";
1456 };
1457
1458 uart1: serial@feb40000 {
1459 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1460 reg = <0x0 0xfeb40000 0x0 0x100>;
1461 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
1462 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1463 clock-names = "baudclk", "apb_pclk";
1464 dmas = <&dmac0 8>, <&dmac0 9>;
1465 dma-names = "tx", "rx";
1466 pinctrl-0 = <&uart1m1_xfer>;
1467 pinctrl-names = "default";
1468 reg-io-width = <4>;
1469 reg-shift = <2>;
1470 status = "disabled";
1471 };
1472
1473 uart2: serial@feb50000 {
1474 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1475 reg = <0x0 0xfeb50000 0x0 0x100>;
1476 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
1477 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1478 clock-names = "baudclk", "apb_pclk";
1479 dmas = <&dmac0 10>, <&dmac0 11>;
1480 dma-names = "tx", "rx";
1481 pinctrl-0 = <&uart2m1_xfer>;
1482 pinctrl-names = "default";
1483 reg-io-width = <4>;
1484 reg-shift = <2>;
1485 status = "disabled";
1486 };
1487
1488 uart3: serial@feb60000 {
1489 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1490 reg = <0x0 0xfeb60000 0x0 0x100>;
1491 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
1492 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1493 clock-names = "baudclk", "apb_pclk";
1494 dmas = <&dmac0 12>, <&dmac0 13>;
1495 dma-names = "tx", "rx";
1496 pinctrl-0 = <&uart3m1_xfer>;
1497 pinctrl-names = "default";
1498 reg-io-width = <4>;
1499 reg-shift = <2>;
1500 status = "disabled";
1501 };
1502
1503 uart4: serial@feb70000 {
1504 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1505 reg = <0x0 0xfeb70000 0x0 0x100>;
1506 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
1507 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1508 clock-names = "baudclk", "apb_pclk";
1509 dmas = <&dmac1 9>, <&dmac1 10>;
1510 dma-names = "tx", "rx";
1511 pinctrl-0 = <&uart4m1_xfer>;
1512 pinctrl-names = "default";
1513 reg-io-width = <4>;
1514 reg-shift = <2>;
1515 status = "disabled";
1516 };
1517
1518 uart5: serial@feb80000 {
1519 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1520 reg = <0x0 0xfeb80000 0x0 0x100>;
1521 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
1522 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1523 clock-names = "baudclk", "apb_pclk";
1524 dmas = <&dmac1 11>, <&dmac1 12>;
1525 dma-names = "tx", "rx";
1526 pinctrl-0 = <&uart5m1_xfer>;
1527 pinctrl-names = "default";
1528 reg-io-width = <4>;
1529 reg-shift = <2>;
1530 status = "disabled";
1531 };
1532
1533 uart6: serial@feb90000 {
1534 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1535 reg = <0x0 0xfeb90000 0x0 0x100>;
1536 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
1537 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1538 clock-names = "baudclk", "apb_pclk";
1539 dmas = <&dmac1 13>, <&dmac1 14>;
1540 dma-names = "tx", "rx";
1541 pinctrl-0 = <&uart6m1_xfer>;
1542 pinctrl-names = "default";
1543 reg-io-width = <4>;
1544 reg-shift = <2>;
1545 status = "disabled";
1546 };
1547
1548 uart7: serial@feba0000 {
1549 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1550 reg = <0x0 0xfeba0000 0x0 0x100>;
1551 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
1552 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1553 clock-names = "baudclk", "apb_pclk";
1554 dmas = <&dmac2 7>, <&dmac2 8>;
1555 dma-names = "tx", "rx";
1556 pinctrl-0 = <&uart7m1_xfer>;
1557 pinctrl-names = "default";
1558 reg-io-width = <4>;
1559 reg-shift = <2>;
1560 status = "disabled";
1561 };
1562
1563 uart8: serial@febb0000 {
1564 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1565 reg = <0x0 0xfebb0000 0x0 0x100>;
1566 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
1567 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1568 clock-names = "baudclk", "apb_pclk";
1569 dmas = <&dmac2 9>, <&dmac2 10>;
1570 dma-names = "tx", "rx";
1571 pinctrl-0 = <&uart8m1_xfer>;
1572 pinctrl-names = "default";
1573 reg-io-width = <4>;
1574 reg-shift = <2>;
1575 status = "disabled";
1576 };
1577
1578 uart9: serial@febc0000 {
1579 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
1580 reg = <0x0 0xfebc0000 0x0 0x100>;
1581 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
1582 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1583 clock-names = "baudclk", "apb_pclk";
1584 dmas = <&dmac2 11>, <&dmac2 12>;
1585 dma-names = "tx", "rx";
1586 pinctrl-0 = <&uart9m1_xfer>;
1587 pinctrl-names = "default";
1588 reg-io-width = <4>;
1589 reg-shift = <2>;
1590 status = "disabled";
1591 };
1592
1593 pwm4: pwm@febd0000 {
1594 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1595 reg = <0x0 0xfebd0000 0x0 0x10>;
1596 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1597 clock-names = "pwm", "pclk";
1598 pinctrl-0 = <&pwm4m0_pins>;
1599 pinctrl-names = "default";
1600 #pwm-cells = <3>;
1601 status = "disabled";
1602 };
1603
1604 pwm5: pwm@febd0010 {
1605 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1606 reg = <0x0 0xfebd0010 0x0 0x10>;
1607 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1608 clock-names = "pwm", "pclk";
1609 pinctrl-0 = <&pwm5m0_pins>;
1610 pinctrl-names = "default";
1611 #pwm-cells = <3>;
1612 status = "disabled";
1613 };
1614
1615 pwm6: pwm@febd0020 {
1616 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1617 reg = <0x0 0xfebd0020 0x0 0x10>;
1618 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1619 clock-names = "pwm", "pclk";
1620 pinctrl-0 = <&pwm6m0_pins>;
1621 pinctrl-names = "default";
1622 #pwm-cells = <3>;
1623 status = "disabled";
1624 };
1625
1626 pwm7: pwm@febd0030 {
1627 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1628 reg = <0x0 0xfebd0030 0x0 0x10>;
1629 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1630 clock-names = "pwm", "pclk";
1631 pinctrl-0 = <&pwm7m0_pins>;
1632 pinctrl-names = "default";
1633 #pwm-cells = <3>;
1634 status = "disabled";
1635 };
1636
1637 pwm8: pwm@febe0000 {
1638 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1639 reg = <0x0 0xfebe0000 0x0 0x10>;
1640 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1641 clock-names = "pwm", "pclk";
1642 pinctrl-0 = <&pwm8m0_pins>;
1643 pinctrl-names = "default";
1644 #pwm-cells = <3>;
1645 status = "disabled";
1646 };
1647
1648 pwm9: pwm@febe0010 {
1649 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1650 reg = <0x0 0xfebe0010 0x0 0x10>;
1651 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1652 clock-names = "pwm", "pclk";
1653 pinctrl-0 = <&pwm9m0_pins>;
1654 pinctrl-names = "default";
1655 #pwm-cells = <3>;
1656 status = "disabled";
1657 };
1658
1659 pwm10: pwm@febe0020 {
1660 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1661 reg = <0x0 0xfebe0020 0x0 0x10>;
1662 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1663 clock-names = "pwm", "pclk";
1664 pinctrl-0 = <&pwm10m0_pins>;
1665 pinctrl-names = "default";
1666 #pwm-cells = <3>;
1667 status = "disabled";
1668 };
1669
1670 pwm11: pwm@febe0030 {
1671 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1672 reg = <0x0 0xfebe0030 0x0 0x10>;
1673 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1674 clock-names = "pwm", "pclk";
1675 pinctrl-0 = <&pwm11m0_pins>;
1676 pinctrl-names = "default";
1677 #pwm-cells = <3>;
1678 status = "disabled";
1679 };
1680
1681 pwm12: pwm@febf0000 {
1682 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1683 reg = <0x0 0xfebf0000 0x0 0x10>;
1684 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1685 clock-names = "pwm", "pclk";
1686 pinctrl-0 = <&pwm12m0_pins>;
1687 pinctrl-names = "default";
1688 #pwm-cells = <3>;
1689 status = "disabled";
1690 };
1691
1692 pwm13: pwm@febf0010 {
1693 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1694 reg = <0x0 0xfebf0010 0x0 0x10>;
1695 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1696 clock-names = "pwm", "pclk";
1697 pinctrl-0 = <&pwm13m0_pins>;
1698 pinctrl-names = "default";
1699 #pwm-cells = <3>;
1700 status = "disabled";
1701 };
1702
1703 pwm14: pwm@febf0020 {
1704 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1705 reg = <0x0 0xfebf0020 0x0 0x10>;
1706 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1707 clock-names = "pwm", "pclk";
1708 pinctrl-0 = <&pwm14m0_pins>;
1709 pinctrl-names = "default";
1710 #pwm-cells = <3>;
1711 status = "disabled";
1712 };
1713
1714 pwm15: pwm@febf0030 {
1715 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
1716 reg = <0x0 0xfebf0030 0x0 0x10>;
1717 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1718 clock-names = "pwm", "pclk";
1719 pinctrl-0 = <&pwm15m0_pins>;
1720 pinctrl-names = "default";
1721 #pwm-cells = <3>;
1722 status = "disabled";
1723 };
1724
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1725 tsadc: tsadc@fec00000 {
1726 compatible = "rockchip,rk3588-tsadc";
1727 reg = <0x0 0xfec00000 0x0 0x400>;
1728 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
1729 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1730 clock-names = "tsadc", "apb_pclk";
1731 assigned-clocks = <&cru CLK_TSADC>;
1732 assigned-clock-rates = <2000000>;
1733 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
1734 reset-names = "tsadc-apb", "tsadc";
1735 rockchip,hw-tshut-temp = <120000>;
1736 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1737 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1738 pinctrl-0 = <&tsadc_gpio_func>;
1739 pinctrl-1 = <&tsadc_shut>;
1740 pinctrl-names = "gpio", "otpout";
1741 #thermal-sensor-cells = <1>;
1742 status = "disabled";
1743 };
1744
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1745 i2c6: i2c@fec80000 {
1746 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1747 reg = <0x0 0xfec80000 0x0 0x1000>;
1748 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1749 clock-names = "i2c", "pclk";
1750 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
1751 pinctrl-0 = <&i2c6m0_xfer>;
1752 pinctrl-names = "default";
1753 #address-cells = <1>;
1754 #size-cells = <0>;
1755 status = "disabled";
1756 };
1757
1758 i2c7: i2c@fec90000 {
1759 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1760 reg = <0x0 0xfec90000 0x0 0x1000>;
1761 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1762 clock-names = "i2c", "pclk";
1763 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1764 pinctrl-0 = <&i2c7m0_xfer>;
1765 pinctrl-names = "default";
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1768 status = "disabled";
1769 };
1770
1771 i2c8: i2c@feca0000 {
1772 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
1773 reg = <0x0 0xfeca0000 0x0 0x1000>;
1774 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
1775 clock-names = "i2c", "pclk";
1776 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
1777 pinctrl-0 = <&i2c8m0_xfer>;
1778 pinctrl-names = "default";
1779 #address-cells = <1>;
1780 #size-cells = <0>;
1781 status = "disabled";
1782 };
1783
1784 spi4: spi@fecb0000 {
1785 compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
1786 reg = <0x0 0xfecb0000 0x0 0x1000>;
1787 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
1788 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
1789 clock-names = "spiclk", "apb_pclk";
1790 dmas = <&dmac2 13>, <&dmac2 14>;
1791 dma-names = "tx", "rx";
1792 num-cs = <2>;
1793 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
1794 pinctrl-names = "default";
1795 #address-cells = <1>;
1796 #size-cells = <0>;
1797 status = "disabled";
1798 };
1799
Eugen Hristev72d61d12023-05-29 10:34:23 +0300[diff] [blame^]1800 otp: efuse@fecc0000 {
1801 compatible = "rockchip,rk3588-otp";
1802 reg = <0x0 0xfecc0000 0x0 0x400>;
1803 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
1804 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
1805 clock-names = "otp", "apb_pclk", "phy", "arb";
1806 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
1807 <&cru SRST_OTPC_ARB>;
1808 reset-names = "otp", "apb", "arb";
1809 #address-cells = <1>;
1810 #size-cells = <1>;
1811
1812 cpu_code: cpu-code@2 {
1813 reg = <0x02 0x2>;
1814 };
1815
1816 otp_id: id@7 {
1817 reg = <0x07 0x10>;
1818 };
1819
1820 cpub0_leakage: cpu-leakage@17 {
1821 reg = <0x17 0x1>;
1822 };
1823
1824 cpub1_leakage: cpu-leakage@18 {
1825 reg = <0x18 0x1>;
1826 };
1827
1828 cpul_leakage: cpu-leakage@19 {
1829 reg = <0x19 0x1>;
1830 };
1831
1832 log_leakage: log-leakage@1a {
1833 reg = <0x1a 0x1>;
1834 };
1835
1836 gpu_leakage: gpu-leakage@1b {
1837 reg = <0x1b 0x1>;
1838 };
1839
1840 otp_cpu_version: cpu-version@1c {
1841 reg = <0x1c 0x1>;
1842 bits = <3 3>;
1843 };
1844
1845 npu_leakage: npu-leakage@28 {
1846 reg = <0x28 0x1>;
1847 };
1848
1849 codec_leakage: codec-leakage@29 {
1850 reg = <0x29 0x1>;
1851 };
1852 };
1853
Jagan Teki3cf5bca2023-01-30 20:27:42 +0530[diff] [blame]1854 dmac2: dma-controller@fed10000 {
1855 compatible = "arm,pl330", "arm,primecell";
1856 reg = <0x0 0xfed10000 0x0 0x4000>;
1857 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
1858 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
1859 arm,pl330-periph-burst;
1860 clocks = <&cru ACLK_DMAC2>;
1861 clock-names = "apb_pclk";
1862 #dma-cells = <1>;
1863 };
1864
1865 system_sram2: sram@ff001000 {
1866 compatible = "mmio-sram";
1867 reg = <0x0 0xff001000 0x0 0xef000>;
1868 ranges = <0x0 0x0 0xff001000 0xef000>;
1869 #address-cells = <1>;
1870 #size-cells = <1>;
1871 };
1872
1873 pinctrl: pinctrl {
1874 compatible = "rockchip,rk3588-pinctrl";
1875 ranges;
1876 rockchip,grf = <&ioc>;
1877 #address-cells = <2>;
1878 #size-cells = <2>;
1879
1880 gpio0: gpio@fd8a0000 {
1881 compatible = "rockchip,gpio-bank";
1882 reg = <0x0 0xfd8a0000 0x0 0x100>;
1883 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
1884 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
1885 gpio-controller;
1886 gpio-ranges = <&pinctrl 0 0 32>;
1887 interrupt-controller;
1888 #gpio-cells = <2>;
1889 #interrupt-cells = <2>;
1890 };
1891
1892 gpio1: gpio@fec20000 {
1893 compatible = "rockchip,gpio-bank";
1894 reg = <0x0 0xfec20000 0x0 0x100>;
1895 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
1896 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1897 gpio-controller;
1898 gpio-ranges = <&pinctrl 0 32 32>;
1899 interrupt-controller;
1900 #gpio-cells = <2>;
1901 #interrupt-cells = <2>;
1902 };
1903
1904 gpio2: gpio@fec30000 {
1905 compatible = "rockchip,gpio-bank";
1906 reg = <0x0 0xfec30000 0x0 0x100>;
1907 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
1908 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1909 gpio-controller;
1910 gpio-ranges = <&pinctrl 0 64 32>;
1911 interrupt-controller;
1912 #gpio-cells = <2>;
1913 #interrupt-cells = <2>;
1914 };
1915
1916 gpio3: gpio@fec40000 {
1917 compatible = "rockchip,gpio-bank";
1918 reg = <0x0 0xfec40000 0x0 0x100>;
1919 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
1920 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1921 gpio-controller;
1922 gpio-ranges = <&pinctrl 0 96 32>;
1923 interrupt-controller;
1924 #gpio-cells = <2>;
1925 #interrupt-cells = <2>;
1926 };
1927
1928 gpio4: gpio@fec50000 {
1929 compatible = "rockchip,gpio-bank";
1930 reg = <0x0 0xfec50000 0x0 0x100>;
1931 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
1932 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1933 gpio-controller;
1934 gpio-ranges = <&pinctrl 0 128 32>;
1935 interrupt-controller;
1936 #gpio-cells = <2>;
1937 #interrupt-cells = <2>;
1938 };
1939 };
1940};
1941
1942#include "rk3588s-pinctrl.dtsi"