Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2011 Michal Simek |
| 4 | * |
| 5 | * Michal SIMEK <monstr@monstr.eu> |
| 6 | * |
| 7 | * Based on Xilinx gmac driver: |
| 8 | * (C) Copyright 2011 Xilinx |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 11 | #include <clk.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 12 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 13 | #include <cpu_func.h> |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 14 | #include <dm.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 15 | #include <net.h> |
Michal Simek | b055f67 | 2014-04-25 14:17:38 +0200 | [diff] [blame] | 16 | #include <netdev.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 17 | #include <config.h> |
Michal Simek | d9cfa97 | 2015-09-24 20:13:45 +0200 | [diff] [blame] | 18 | #include <console.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 19 | #include <malloc.h> |
| 20 | #include <asm/io.h> |
| 21 | #include <phy.h> |
| 22 | #include <miiphy.h> |
Mateusz Kulikowski | 93597d7 | 2016-01-23 11:54:33 +0100 | [diff] [blame] | 23 | #include <wait_bit.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 24 | #include <watchdog.h> |
Siva Durga Prasad Paladugu | 2b0690e | 2014-12-06 12:57:53 +0530 | [diff] [blame] | 25 | #include <asm/system.h> |
David Andrey | 73875dc | 2013-04-05 17:24:24 +0200 | [diff] [blame] | 26 | #include <asm/arch/hardware.h> |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 27 | #include <asm/arch/sys_proto.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 28 | #include <dm/device_compat.h> |
Simon Glass | d66c5f7 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 29 | #include <linux/err.h> |
Masahiro Yamada | 64e4f7f | 2016-09-21 11:28:57 +0900 | [diff] [blame] | 30 | #include <linux/errno.h> |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 31 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 32 | /* Bit/mask specification */ |
| 33 | #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */ |
| 34 | #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */ |
| 35 | #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */ |
| 36 | #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */ |
| 37 | #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */ |
| 38 | |
| 39 | #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */ |
| 40 | #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */ |
| 41 | #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */ |
| 42 | |
| 43 | #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */ |
| 44 | #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */ |
| 45 | #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */ |
| 46 | |
| 47 | /* Wrap bit, last descriptor */ |
| 48 | #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 |
| 49 | #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 50 | #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 51 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 52 | #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ |
| 53 | #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ |
| 54 | #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ |
| 55 | #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ |
| 56 | |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 57 | #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ |
| 58 | #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ |
| 59 | #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ |
| 60 | #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ |
Siva Durga Prasad Paladugu | f6c2d20 | 2016-05-16 15:31:38 +0530 | [diff] [blame] | 61 | #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 62 | #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 63 | #ifdef CONFIG_ARM64 |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 64 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 65 | #else |
Siva Durga Prasad Paladugu | 7e7fcc3 | 2016-05-16 15:31:37 +0530 | [diff] [blame] | 66 | #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ |
Michal Simek | 780c535 | 2015-09-08 17:20:01 +0200 | [diff] [blame] | 67 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 68 | |
Siva Durga Prasad Paladugu | 71245a4 | 2014-07-08 15:31:03 +0530 | [diff] [blame] | 69 | #ifdef CONFIG_ARM64 |
| 70 | # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ |
| 71 | #else |
| 72 | # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */ |
| 73 | #endif |
| 74 | |
| 75 | #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \ |
| 76 | ZYNQ_GEM_NWCFG_FDEN | \ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 77 | ZYNQ_GEM_NWCFG_FSREM | \ |
| 78 | ZYNQ_GEM_NWCFG_MDCCLKDIV) |
| 79 | |
| 80 | #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */ |
| 81 | |
| 82 | #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */ |
| 83 | /* Use full configured addressable space (8 Kb) */ |
| 84 | #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300 |
| 85 | /* Use full configured addressable space (4 Kb) */ |
| 86 | #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400 |
| 87 | /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */ |
| 88 | #define ZYNQ_GEM_DMACR_RXBUF 0x00180000 |
| 89 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 90 | #if defined(CONFIG_PHYS_64BIT) |
| 91 | # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */ |
| 92 | #else |
| 93 | # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */ |
| 94 | #endif |
| 95 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 96 | #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \ |
| 97 | ZYNQ_GEM_DMACR_RXSIZE | \ |
| 98 | ZYNQ_GEM_DMACR_TXSIZE | \ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 99 | ZYNQ_GEM_DMACR_RXBUF | \ |
| 100 | ZYNQ_GEM_DMA_BUS_WIDTH) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 101 | |
Michal Simek | 975ae35 | 2015-08-17 09:57:46 +0200 | [diff] [blame] | 102 | #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ |
| 103 | |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 104 | #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 |
| 105 | |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 106 | #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23) |
| 107 | |
Michal Simek | ab72cb4 | 2013-04-22 14:41:09 +0200 | [diff] [blame] | 108 | /* Use MII register 1 (MII status register) to detect PHY */ |
| 109 | #define PHY_DETECT_REG 1 |
| 110 | |
| 111 | /* Mask used to verify certain PHY features (or register contents) |
| 112 | * in the register above: |
| 113 | * 0x1000: 10Mbps full duplex support |
| 114 | * 0x0800: 10Mbps half duplex support |
| 115 | * 0x0008: Auto-negotiation support |
| 116 | */ |
| 117 | #define PHY_DETECT_MASK 0x1808 |
| 118 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 119 | /* TX BD status masks */ |
| 120 | #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff |
| 121 | #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 |
| 122 | #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 |
| 123 | |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 124 | /* Clock frequencies for different speeds */ |
| 125 | #define ZYNQ_GEM_FREQUENCY_10 2500000UL |
| 126 | #define ZYNQ_GEM_FREQUENCY_100 25000000UL |
| 127 | #define ZYNQ_GEM_FREQUENCY_1000 125000000UL |
| 128 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 129 | /* Device registers */ |
| 130 | struct zynq_gem_regs { |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 131 | u32 nwctrl; /* 0x0 - Network Control reg */ |
| 132 | u32 nwcfg; /* 0x4 - Network Config reg */ |
| 133 | u32 nwsr; /* 0x8 - Network Status reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 134 | u32 reserved1; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 135 | u32 dmacr; /* 0x10 - DMA Control reg */ |
| 136 | u32 txsr; /* 0x14 - TX Status reg */ |
| 137 | u32 rxqbase; /* 0x18 - RX Q Base address reg */ |
| 138 | u32 txqbase; /* 0x1c - TX Q Base address reg */ |
| 139 | u32 rxsr; /* 0x20 - RX Status reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 140 | u32 reserved2[2]; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 141 | u32 idr; /* 0x2c - Interrupt Disable reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 142 | u32 reserved3; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 143 | u32 phymntnc; /* 0x34 - Phy Maintaince reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 144 | u32 reserved4[18]; |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 145 | u32 hashl; /* 0x80 - Hash Low address reg */ |
| 146 | u32 hashh; /* 0x84 - Hash High address reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 147 | #define LADDR_LOW 0 |
| 148 | #define LADDR_HIGH 1 |
Michal Simek | 74a86e8 | 2015-10-05 11:49:43 +0200 | [diff] [blame] | 149 | u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */ |
| 150 | u32 match[4]; /* 0xa8 - Type ID1 Match reg */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 151 | u32 reserved6[18]; |
Michal Simek | ff5dbef | 2015-10-05 12:49:48 +0200 | [diff] [blame] | 152 | #define STAT_SIZE 44 |
| 153 | u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 154 | u32 reserved9[20]; |
| 155 | u32 pcscntrl; |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 156 | u32 rserved12[36]; |
| 157 | u32 dcfg6; /* 0x294 Design config reg6 */ |
| 158 | u32 reserved7[106]; |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 159 | u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ |
| 160 | u32 reserved8[15]; |
| 161 | u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 162 | u32 reserved10[17]; |
| 163 | u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */ |
| 164 | u32 reserved11[2]; |
| 165 | u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */ |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | /* BD descriptors */ |
| 169 | struct emac_bd { |
| 170 | u32 addr; /* Next descriptor pointer */ |
| 171 | u32 status; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 172 | #if defined(CONFIG_PHYS_64BIT) |
| 173 | u32 addr_hi; |
| 174 | u32 reserved; |
| 175 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 176 | }; |
| 177 | |
Michal Simek | c40c93e | 2019-05-22 14:12:20 +0200 | [diff] [blame] | 178 | /* Reduce amount of BUFs if you have limited amount of memory */ |
Siva Durga Prasad Paladugu | 55931cf | 2015-04-15 12:15:01 +0530 | [diff] [blame] | 179 | #define RX_BUF 32 |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 180 | /* Page table entries are set to 1MB, or multiples of 1MB |
| 181 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. |
| 182 | */ |
| 183 | #define BD_SPACE 0x100000 |
| 184 | /* BD separation space */ |
Michal Simek | c6eb0bc | 2015-08-17 09:45:53 +0200 | [diff] [blame] | 185 | #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd)) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 186 | |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 187 | /* Setup the first free TX descriptor */ |
| 188 | #define TX_FREE_DESC 2 |
| 189 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 190 | /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ |
| 191 | struct zynq_gem_priv { |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 192 | struct emac_bd *tx_bd; |
| 193 | struct emac_bd *rx_bd; |
| 194 | char *rxbuffers; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 195 | u32 rxbd_current; |
| 196 | u32 rx_first_buf; |
| 197 | int phyaddr; |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 198 | int init; |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 199 | struct zynq_gem_regs *iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 200 | struct zynq_gem_regs *mdiobase; |
Michal Simek | 492de0f | 2015-10-07 16:42:56 +0200 | [diff] [blame] | 201 | phy_interface_t interface; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 202 | struct phy_device *phydev; |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 203 | ofnode phy_of_node; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 204 | struct mii_dev *bus; |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 205 | struct clk clk; |
Siva Durga Prasad Paladugu | 0703cc5 | 2018-04-12 12:22:17 +0200 | [diff] [blame] | 206 | u32 max_speed; |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 207 | bool int_pcs; |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 208 | bool dma_64bit; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 209 | }; |
| 210 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 211 | static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 212 | u32 op, u16 *data) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 213 | { |
| 214 | u32 mgtcr; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 215 | struct zynq_gem_regs *regs = priv->mdiobase; |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 216 | int err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 217 | |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 218 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
| 219 | true, 20000, false); |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 220 | if (err) |
| 221 | return err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 222 | |
| 223 | /* Construct mgtcr mask for the operation */ |
| 224 | mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | |
| 225 | (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) | |
| 226 | (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data; |
| 227 | |
| 228 | /* Write mgtcr and wait for completion */ |
| 229 | writel(mgtcr, ®s->phymntnc); |
| 230 | |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 231 | err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, |
| 232 | true, 20000, false); |
Michal Simek | e670965 | 2016-12-12 09:47:26 +0100 | [diff] [blame] | 233 | if (err) |
| 234 | return err; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 235 | |
| 236 | if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) |
| 237 | *data = readl(®s->phymntnc); |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 242 | static int phyread(struct zynq_gem_priv *priv, u32 phy_addr, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 243 | u32 regnum, u16 *val) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 244 | { |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 245 | int ret; |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 246 | |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 247 | ret = phy_setup_op(priv, phy_addr, regnum, |
| 248 | ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val); |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 249 | |
| 250 | if (!ret) |
| 251 | debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__, |
| 252 | phy_addr, regnum, *val); |
| 253 | |
| 254 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 255 | } |
| 256 | |
Michal Simek | 70551ca | 2018-06-13 10:00:30 +0200 | [diff] [blame] | 257 | static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr, |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 258 | u32 regnum, u16 data) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 259 | { |
Michal Simek | c919c2c | 2015-10-07 16:34:51 +0200 | [diff] [blame] | 260 | debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr, |
| 261 | regnum, data); |
| 262 | |
Michal Simek | 1a63ee2 | 2015-11-30 10:24:15 +0100 | [diff] [blame] | 263 | return phy_setup_op(priv, phy_addr, regnum, |
| 264 | ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 265 | } |
| 266 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 267 | static int zynq_gem_setup_mac(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 268 | { |
| 269 | u32 i, macaddrlow, macaddrhigh; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 270 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 271 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 272 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 273 | |
| 274 | /* Set the MAC bits [31:0] in BOT */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 275 | macaddrlow = pdata->enetaddr[0]; |
| 276 | macaddrlow |= pdata->enetaddr[1] << 8; |
| 277 | macaddrlow |= pdata->enetaddr[2] << 16; |
| 278 | macaddrlow |= pdata->enetaddr[3] << 24; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 279 | |
| 280 | /* Set MAC bits [47:32] in TOP */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 281 | macaddrhigh = pdata->enetaddr[4]; |
| 282 | macaddrhigh |= pdata->enetaddr[5] << 8; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 283 | |
| 284 | for (i = 0; i < 4; i++) { |
| 285 | writel(0, ®s->laddr[i][LADDR_LOW]); |
| 286 | writel(0, ®s->laddr[i][LADDR_HIGH]); |
| 287 | /* Do not use MATCHx register */ |
| 288 | writel(0, ®s->match[i]); |
| 289 | } |
| 290 | |
| 291 | writel(macaddrlow, ®s->laddr[0][LADDR_LOW]); |
| 292 | writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 297 | static int zynq_phy_init(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 298 | { |
Michal Simek | 75fbb69 | 2015-11-30 13:38:32 +0100 | [diff] [blame] | 299 | int ret; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 300 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 301 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 302 | const u32 supported = SUPPORTED_10baseT_Half | |
| 303 | SUPPORTED_10baseT_Full | |
| 304 | SUPPORTED_100baseT_Half | |
| 305 | SUPPORTED_100baseT_Full | |
| 306 | SUPPORTED_1000baseT_Half | |
| 307 | SUPPORTED_1000baseT_Full; |
| 308 | |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 309 | /* Enable only MDIO bus */ |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 310 | writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 311 | |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 312 | priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, |
| 313 | priv->interface); |
Michal Simek | 2c68e08 | 2015-11-30 14:03:37 +0100 | [diff] [blame] | 314 | if (!priv->phydev) |
| 315 | return -ENODEV; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 316 | |
Siva Durga Prasad Paladugu | 0703cc5 | 2018-04-12 12:22:17 +0200 | [diff] [blame] | 317 | if (priv->max_speed) { |
| 318 | ret = phy_set_supported(priv->phydev, priv->max_speed); |
| 319 | if (ret) |
| 320 | return ret; |
| 321 | } |
| 322 | |
Siva Durga Prasad Paladugu | 1220350 | 2019-03-27 17:39:59 +0530 | [diff] [blame] | 323 | priv->phydev->supported &= supported | ADVERTISED_Pause | |
| 324 | ADVERTISED_Asym_Pause; |
| 325 | |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 326 | priv->phydev->advertising = priv->phydev->supported; |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 327 | priv->phydev->node = priv->phy_of_node; |
Dan Murphy | a582871 | 2016-05-02 15:45:57 -0500 | [diff] [blame] | 328 | |
Michal Simek | 24ce232 | 2016-05-18 14:37:23 +0200 | [diff] [blame] | 329 | return phy_config(priv->phydev); |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 330 | } |
| 331 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 332 | static int zynq_gem_init(struct udevice *dev) |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 333 | { |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 334 | u32 i, nwconfig; |
Michal Simek | dbc0cfc | 2016-05-18 12:37:22 +0200 | [diff] [blame] | 335 | int ret; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 336 | unsigned long clk_rate = 0; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 337 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 338 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 339 | struct zynq_gem_regs *regs_mdio = priv->mdiobase; |
Michal Simek | 7cd7ea6 | 2015-11-30 13:54:43 +0100 | [diff] [blame] | 340 | struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; |
| 341 | struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; |
| 342 | |
Siva Durga Prasad Paladugu | b7b3637 | 2018-11-26 16:27:39 +0530 | [diff] [blame] | 343 | if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B) |
| 344 | priv->dma_64bit = true; |
| 345 | else |
| 346 | priv->dma_64bit = false; |
| 347 | |
| 348 | #if defined(CONFIG_PHYS_64BIT) |
| 349 | if (!priv->dma_64bit) { |
| 350 | printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n", |
| 351 | __func__); |
| 352 | return -EINVAL; |
| 353 | } |
| 354 | #else |
| 355 | if (priv->dma_64bit) |
| 356 | debug("WARN: %s: Not using 64-bit dma even HW supports it\n", |
| 357 | __func__); |
| 358 | #endif |
| 359 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 360 | if (!priv->init) { |
| 361 | /* Disable all interrupts */ |
| 362 | writel(0xFFFFFFFF, ®s->idr); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 363 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 364 | /* Disable the receiver & transmitter */ |
| 365 | writel(0, ®s->nwctrl); |
| 366 | writel(0, ®s->txsr); |
| 367 | writel(0, ®s->rxsr); |
| 368 | writel(0, ®s->phymntnc); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 369 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 370 | /* Clear the Hash registers for the mac address |
| 371 | * pointed by AddressPtr |
| 372 | */ |
| 373 | writel(0x0, ®s->hashl); |
| 374 | /* Write bits [63:32] in TOP */ |
| 375 | writel(0x0, ®s->hashh); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 376 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 377 | /* Clear all counters */ |
Michal Simek | ff5dbef | 2015-10-05 12:49:48 +0200 | [diff] [blame] | 378 | for (i = 0; i < STAT_SIZE; i++) |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 379 | readl(®s->stat[i]); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 380 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 381 | /* Setup RxBD space */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 382 | memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 383 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 384 | for (i = 0; i < RX_BUF; i++) { |
| 385 | priv->rx_bd[i].status = 0xF0000000; |
| 386 | priv->rx_bd[i].addr = |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 387 | (lower_32_bits((ulong)(priv->rxbuffers) |
| 388 | + (i * PKTSIZE_ALIGN))); |
| 389 | #if defined(CONFIG_PHYS_64BIT) |
| 390 | priv->rx_bd[i].addr_hi = |
| 391 | (upper_32_bits((ulong)(priv->rxbuffers) |
| 392 | + (i * PKTSIZE_ALIGN))); |
| 393 | #endif |
| 394 | } |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 395 | /* WRAP bit to last BD */ |
| 396 | priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; |
| 397 | /* Write RxBDs to IP */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 398 | writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase); |
| 399 | #if defined(CONFIG_PHYS_64BIT) |
| 400 | writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase); |
| 401 | #endif |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 402 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 403 | /* Setup for DMA Configuration register */ |
| 404 | writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 405 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 406 | /* Setup for Network Control register, MDIO, Rx and Tx enable */ |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 407 | setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 408 | |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 409 | /* Disable the second priority queue */ |
| 410 | dummy_tx_bd->addr = 0; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 411 | #if defined(CONFIG_PHYS_64BIT) |
| 412 | dummy_tx_bd->addr_hi = 0; |
| 413 | #endif |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 414 | dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
| 415 | ZYNQ_GEM_TXBUF_LAST_MASK| |
| 416 | ZYNQ_GEM_TXBUF_USED_MASK; |
| 417 | |
| 418 | dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | |
| 419 | ZYNQ_GEM_RXBUF_NEW_MASK; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 420 | #if defined(CONFIG_PHYS_64BIT) |
| 421 | dummy_rx_bd->addr_hi = 0; |
| 422 | #endif |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 423 | dummy_rx_bd->status = 0; |
Edgar E. Iglesias | 2304511 | 2015-09-25 23:50:07 -0700 | [diff] [blame] | 424 | |
| 425 | writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); |
| 426 | writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); |
| 427 | |
Michal Simek | a94f84d | 2013-01-24 13:04:12 +0100 | [diff] [blame] | 428 | priv->init++; |
| 429 | } |
| 430 | |
Michal Simek | dbc0cfc | 2016-05-18 12:37:22 +0200 | [diff] [blame] | 431 | ret = phy_startup(priv->phydev); |
| 432 | if (ret) |
| 433 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 434 | |
Michal Simek | 43b3832 | 2015-11-30 13:44:49 +0100 | [diff] [blame] | 435 | if (!priv->phydev->link) { |
| 436 | printf("%s: No link.\n", priv->phydev->dev->name); |
Michal Simek | 216b96d | 2013-11-12 14:25:29 +0100 | [diff] [blame] | 437 | return -1; |
| 438 | } |
| 439 | |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 440 | nwconfig = ZYNQ_GEM_NWCFG_INIT; |
| 441 | |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 442 | /* |
| 443 | * Set SGMII enable PCS selection only if internal PCS/PMA |
| 444 | * core is used and interface is SGMII. |
| 445 | */ |
| 446 | if (priv->interface == PHY_INTERFACE_MODE_SGMII && |
| 447 | priv->int_pcs) { |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 448 | nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | |
| 449 | ZYNQ_GEM_NWCFG_PCS_SEL; |
Siva Durga Prasad Paladugu | 4546700 | 2016-03-25 12:53:44 +0530 | [diff] [blame] | 450 | #ifdef CONFIG_ARM64 |
| 451 | writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, |
| 452 | ®s->pcscntrl); |
| 453 | #endif |
| 454 | } |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 455 | |
Michal Simek | 43b3832 | 2015-11-30 13:44:49 +0100 | [diff] [blame] | 456 | switch (priv->phydev->speed) { |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 457 | case SPEED_1000: |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 458 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 459 | ®s->nwcfg); |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 460 | clk_rate = ZYNQ_GEM_FREQUENCY_1000; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 461 | break; |
| 462 | case SPEED_100: |
Siva Durga Prasad Paladugu | 65d3f3a | 2016-02-05 13:22:11 +0530 | [diff] [blame] | 463 | writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, |
Michal Simek | 6429595 | 2015-09-08 16:55:42 +0200 | [diff] [blame] | 464 | ®s->nwcfg); |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 465 | clk_rate = ZYNQ_GEM_FREQUENCY_100; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 466 | break; |
| 467 | case SPEED_10: |
Soren Brinkmann | 4dded98 | 2013-11-21 13:39:01 -0800 | [diff] [blame] | 468 | clk_rate = ZYNQ_GEM_FREQUENCY_10; |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 469 | break; |
| 470 | } |
David Andrey | 73875dc | 2013-04-05 17:24:24 +0200 | [diff] [blame] | 471 | |
Stefan Herbrechtsmeier | bb43397 | 2017-01-17 16:27:25 +0100 | [diff] [blame] | 472 | ret = clk_set_rate(&priv->clk, clk_rate); |
| 473 | if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { |
| 474 | dev_err(dev, "failed to set tx clock rate\n"); |
| 475 | return ret; |
| 476 | } |
| 477 | |
| 478 | ret = clk_enable(&priv->clk); |
| 479 | if (ret && ret != -ENOSYS) { |
| 480 | dev_err(dev, "failed to enable tx clock\n"); |
| 481 | return ret; |
| 482 | } |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 483 | |
| 484 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
| 485 | ZYNQ_GEM_NWCTRL_TXEN_MASK); |
| 486 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 487 | return 0; |
| 488 | } |
| 489 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 490 | static int zynq_gem_send(struct udevice *dev, void *ptr, int len) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 491 | { |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 492 | dma_addr_t addr; |
| 493 | u32 size; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 494 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 495 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 496 | struct emac_bd *current_bd = &priv->tx_bd[1]; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 497 | |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 498 | /* Setup Tx BD */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 499 | memset(priv->tx_bd, 0, sizeof(struct emac_bd)); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 500 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 501 | priv->tx_bd->addr = lower_32_bits((ulong)ptr); |
| 502 | #if defined(CONFIG_PHYS_64BIT) |
| 503 | priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr); |
| 504 | #endif |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 505 | priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 506 | ZYNQ_GEM_TXBUF_LAST_MASK; |
| 507 | /* Dummy descriptor to mark it as the last in descriptor chain */ |
| 508 | current_bd->addr = 0x0; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 509 | #if defined(CONFIG_PHYS_64BIT) |
| 510 | current_bd->addr_hi = 0x0; |
| 511 | #endif |
Michal Simek | 1dc446e | 2015-08-17 09:58:54 +0200 | [diff] [blame] | 512 | current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK | |
| 513 | ZYNQ_GEM_TXBUF_LAST_MASK| |
| 514 | ZYNQ_GEM_TXBUF_USED_MASK; |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 515 | |
Michal Simek | b6fe7ad | 2015-08-17 09:50:09 +0200 | [diff] [blame] | 516 | /* setup BD */ |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 517 | writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase); |
| 518 | #if defined(CONFIG_PHYS_64BIT) |
| 519 | writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase); |
| 520 | #endif |
Michal Simek | b6fe7ad | 2015-08-17 09:50:09 +0200 | [diff] [blame] | 521 | |
Prabhakar Kushwaha | 1e9e619 | 2015-10-25 13:18:54 +0530 | [diff] [blame] | 522 | addr = (ulong) ptr; |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 523 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
| 524 | size = roundup(len, ARCH_DMA_MINALIGN); |
| 525 | flush_dcache_range(addr, addr + size); |
| 526 | barrier(); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 527 | |
| 528 | /* Start transmit */ |
| 529 | setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); |
| 530 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 531 | /* Read TX BD status */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 532 | if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) |
| 533 | printf("TX buffers exhausted in mid frame\n"); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 534 | |
Álvaro Fernández Rojas | 918de03 | 2018-01-23 17:14:55 +0100 | [diff] [blame] | 535 | return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, |
| 536 | true, 20000, true); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 537 | } |
| 538 | |
| 539 | /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 540 | static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 541 | { |
| 542 | int frame_len; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 543 | dma_addr_t addr; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 544 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 545 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 546 | |
| 547 | if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK)) |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 548 | return -1; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 549 | |
| 550 | if (!(current_bd->status & |
| 551 | (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) { |
| 552 | printf("GEM: SOF or EOF not set for last buffer received!\n"); |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 553 | return -1; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 557 | if (!frame_len) { |
| 558 | printf("%s: Zero size packet?\n", __func__); |
| 559 | return -1; |
| 560 | } |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 561 | |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 562 | #if defined(CONFIG_PHYS_64BIT) |
| 563 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) |
| 564 | | ((dma_addr_t)current_bd->addr_hi << 32)); |
| 565 | #else |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 566 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 567 | #endif |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 568 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
Vipul Kumar | cbc2ed6 | 2018-11-26 16:27:38 +0530 | [diff] [blame] | 569 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 570 | *packetp = (uchar *)(uintptr_t)addr; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 571 | |
Stefan Theil | 0f407c9 | 2018-12-17 09:12:30 +0100 | [diff] [blame] | 572 | invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
| 573 | barrier(); |
| 574 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 575 | return frame_len; |
| 576 | } |
| 577 | |
| 578 | static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 579 | { |
| 580 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 581 | struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; |
| 582 | struct emac_bd *first_bd; |
Ashok Reddy Soma | 4757253 | 2020-02-23 08:01:29 -0700 | [diff] [blame] | 583 | dma_addr_t addr; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 584 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 585 | if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { |
| 586 | priv->rx_first_buf = priv->rxbd_current; |
| 587 | } else { |
| 588 | current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; |
| 589 | current_bd->status = 0xF0000000; /* FIXME */ |
| 590 | } |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 591 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 592 | if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) { |
| 593 | first_bd = &priv->rx_bd[priv->rx_first_buf]; |
| 594 | first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK; |
| 595 | first_bd->status = 0xF0000000; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 596 | } |
| 597 | |
Ashok Reddy Soma | 4757253 | 2020-02-23 08:01:29 -0700 | [diff] [blame] | 598 | /* Flush the cache for the packet as well */ |
| 599 | #if defined(CONFIG_PHYS_64BIT) |
| 600 | addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) |
| 601 | | ((dma_addr_t)current_bd->addr_hi << 32)); |
| 602 | #else |
| 603 | addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; |
| 604 | #endif |
| 605 | flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, |
| 606 | ARCH_DMA_MINALIGN)); |
| 607 | barrier(); |
| 608 | |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 609 | if ((++priv->rxbd_current) >= RX_BUF) |
| 610 | priv->rxbd_current = 0; |
| 611 | |
Michal Simek | 139f410 | 2015-12-09 14:16:32 +0100 | [diff] [blame] | 612 | return 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 613 | } |
| 614 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 615 | static void zynq_gem_halt(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 616 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 617 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 618 | struct zynq_gem_regs *regs = priv->iobase; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 619 | |
Michal Simek | d9f2c11 | 2012-10-15 14:01:23 +0200 | [diff] [blame] | 620 | clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | |
| 621 | ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 622 | } |
| 623 | |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 624 | __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) |
| 625 | { |
| 626 | return -ENOSYS; |
| 627 | } |
| 628 | |
| 629 | static int zynq_gem_read_rom_mac(struct udevice *dev) |
| 630 | { |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 631 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 632 | |
Olliver Schinagl | fee13c3 | 2017-04-03 16:18:53 +0200 | [diff] [blame] | 633 | if (!pdata) |
| 634 | return -ENOSYS; |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 635 | |
Olliver Schinagl | fee13c3 | 2017-04-03 16:18:53 +0200 | [diff] [blame] | 636 | return zynq_board_read_rom_ethaddr(pdata->enetaddr); |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 637 | } |
| 638 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 639 | static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, |
| 640 | int devad, int reg) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 641 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 642 | struct zynq_gem_priv *priv = bus->priv; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 643 | int ret; |
Michal Simek | d061bfd | 2018-06-14 09:08:44 +0200 | [diff] [blame] | 644 | u16 val = 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 645 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 646 | ret = phyread(priv, addr, reg, &val); |
| 647 | debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret); |
| 648 | return val; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 649 | } |
| 650 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 651 | static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad, |
| 652 | int reg, u16 value) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 653 | { |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 654 | struct zynq_gem_priv *priv = bus->priv; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 655 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 656 | debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value); |
| 657 | return phywrite(priv, addr, reg, value); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 658 | } |
| 659 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 660 | static int zynq_gem_probe(struct udevice *dev) |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 661 | { |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 662 | void *bd_space; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 663 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
| 664 | int ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 665 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 666 | /* Align rxbuffers to ARCH_DMA_MINALIGN */ |
| 667 | priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); |
Michal Simek | c8959f4 | 2018-06-13 15:20:35 +0200 | [diff] [blame] | 668 | if (!priv->rxbuffers) |
| 669 | return -ENOMEM; |
| 670 | |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 671 | memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); |
T Karthik Reddy | 60bf216 | 2020-01-15 02:15:13 -0700 | [diff] [blame] | 672 | ulong addr = (ulong)priv->rxbuffers; |
Stefan Theil | 0f407c9 | 2018-12-17 09:12:30 +0100 | [diff] [blame] | 673 | flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN)); |
| 674 | barrier(); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 675 | |
Siva Durga Prasad Paladugu | 2b0690e | 2014-12-06 12:57:53 +0530 | [diff] [blame] | 676 | /* Align bd_space to MMU_SECTION_SHIFT */ |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 677 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 678 | if (!bd_space) { |
| 679 | ret = -ENOMEM; |
| 680 | goto err1; |
| 681 | } |
Michal Simek | c8959f4 | 2018-06-13 15:20:35 +0200 | [diff] [blame] | 682 | |
Michal Simek | 0afb6b2 | 2015-04-15 13:31:28 +0200 | [diff] [blame] | 683 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, |
| 684 | BD_SPACE, DCACHE_OFF); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 685 | |
| 686 | /* Initialize the bd spaces for tx and rx bd's */ |
| 687 | priv->tx_bd = (struct emac_bd *)bd_space; |
Prabhakar Kushwaha | 1e9e619 | 2015-10-25 13:18:54 +0530 | [diff] [blame] | 688 | priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); |
Srikanth Thokala | cbf20b2 | 2013-11-08 22:55:48 +0530 | [diff] [blame] | 689 | |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 690 | ret = clk_get_by_name(dev, "tx_clk", &priv->clk); |
| 691 | if (ret < 0) { |
| 692 | dev_err(dev, "failed to get clock\n"); |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 693 | goto err1; |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 694 | } |
Siva Durga Prasad Paladugu | baa2035 | 2016-11-15 16:15:42 +0530 | [diff] [blame] | 695 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 696 | priv->bus = mdio_alloc(); |
| 697 | priv->bus->read = zynq_gem_miiphy_read; |
| 698 | priv->bus->write = zynq_gem_miiphy_write; |
| 699 | priv->bus->priv = priv; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 700 | |
Michal Simek | e4dab43 | 2016-12-08 10:25:44 +0100 | [diff] [blame] | 701 | ret = mdio_register_seq(priv->bus, dev->seq); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 702 | if (ret) |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 703 | goto err2; |
| 704 | |
| 705 | ret = zynq_phy_init(dev); |
| 706 | if (ret) |
| 707 | goto err2; |
| 708 | |
| 709 | return ret; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 710 | |
Michal Simek | 049c65b | 2020-02-06 14:36:46 +0100 | [diff] [blame] | 711 | err2: |
| 712 | free(priv->rxbuffers); |
| 713 | err1: |
| 714 | free(priv->tx_bd); |
| 715 | return ret; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 716 | } |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 717 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 718 | static int zynq_gem_remove(struct udevice *dev) |
| 719 | { |
| 720 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 721 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 722 | free(priv->phydev); |
| 723 | mdio_unregister(priv->bus); |
| 724 | mdio_free(priv->bus); |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 725 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 726 | return 0; |
| 727 | } |
| 728 | |
| 729 | static const struct eth_ops zynq_gem_ops = { |
| 730 | .start = zynq_gem_init, |
| 731 | .send = zynq_gem_send, |
| 732 | .recv = zynq_gem_recv, |
Michal Simek | 57b0269 | 2015-12-09 14:26:48 +0100 | [diff] [blame] | 733 | .free_pkt = zynq_gem_free_pkt, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 734 | .stop = zynq_gem_halt, |
| 735 | .write_hwaddr = zynq_gem_setup_mac, |
Joe Hershberger | 7f4e555 | 2016-01-26 11:57:03 -0600 | [diff] [blame] | 736 | .read_rom_hwaddr = zynq_gem_read_rom_mac, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 737 | }; |
Michal Simek | e9ecc1c | 2015-11-30 13:58:36 +0100 | [diff] [blame] | 738 | |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 739 | static int zynq_gem_ofdata_to_platdata(struct udevice *dev) |
| 740 | { |
| 741 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 742 | struct zynq_gem_priv *priv = dev_get_priv(dev); |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 743 | struct ofnode_phandle_args phandle_args; |
Michal Simek | 3c4ce3c | 2015-11-30 14:17:50 +0100 | [diff] [blame] | 744 | const char *phy_mode; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 745 | |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 746 | pdata->iobase = (phys_addr_t)dev_read_addr(dev); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 747 | priv->iobase = (struct zynq_gem_regs *)pdata->iobase; |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 748 | priv->mdiobase = priv->iobase; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 749 | /* Hardcode for now */ |
Michal Simek | c6aa413 | 2015-12-09 09:29:12 +0100 | [diff] [blame] | 750 | priv->phyaddr = -1; |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 751 | |
Michal Simek | 8114538 | 2018-09-20 09:42:27 +0200 | [diff] [blame] | 752 | if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, |
| 753 | &phandle_args)) { |
| 754 | debug("phy-handle does exist %s\n", dev->name); |
| 755 | priv->phyaddr = ofnode_read_u32_default(phandle_args.node, |
| 756 | "reg", -1); |
| 757 | priv->phy_of_node = phandle_args.node; |
| 758 | priv->max_speed = ofnode_read_u32_default(phandle_args.node, |
| 759 | "max-speed", |
| 760 | SPEED_1000); |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 761 | } |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 762 | |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 763 | phy_mode = dev_read_prop(dev, "phy-mode", NULL); |
Michal Simek | 3c4ce3c | 2015-11-30 14:17:50 +0100 | [diff] [blame] | 764 | if (phy_mode) |
| 765 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 766 | if (pdata->phy_interface == -1) { |
| 767 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
| 768 | return -EINVAL; |
| 769 | } |
| 770 | priv->interface = pdata->phy_interface; |
| 771 | |
Siva Durga Prasad Paladugu | 34a48e5 | 2018-07-16 18:25:45 +0530 | [diff] [blame] | 772 | priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); |
Siva Durga Prasad Paladugu | 134cfa6 | 2017-11-23 12:56:55 +0530 | [diff] [blame] | 773 | |
Michal Simek | 55ee186 | 2016-05-30 10:43:11 +0200 | [diff] [blame] | 774 | printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n", |
| 775 | (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr, |
| 776 | phy_string_for_interface(priv->interface)); |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 777 | |
| 778 | return 0; |
Michal Simek | 19dfc47 | 2012-09-13 20:23:34 +0000 | [diff] [blame] | 779 | } |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 780 | |
| 781 | static const struct udevice_id zynq_gem_ids[] = { |
Siva Durga Prasad Paladugu | 3d61161 | 2019-07-25 23:07:59 -0700 | [diff] [blame] | 782 | { .compatible = "cdns,versal-gem" }, |
Michal Simek | 250e05e | 2015-11-30 14:14:56 +0100 | [diff] [blame] | 783 | { .compatible = "cdns,zynqmp-gem" }, |
| 784 | { .compatible = "cdns,zynq-gem" }, |
| 785 | { .compatible = "cdns,gem" }, |
| 786 | { } |
| 787 | }; |
| 788 | |
| 789 | U_BOOT_DRIVER(zynq_gem) = { |
| 790 | .name = "zynq_gem", |
| 791 | .id = UCLASS_ETH, |
| 792 | .of_match = zynq_gem_ids, |
| 793 | .ofdata_to_platdata = zynq_gem_ofdata_to_platdata, |
| 794 | .probe = zynq_gem_probe, |
| 795 | .remove = zynq_gem_remove, |
| 796 | .ops = &zynq_gem_ops, |
| 797 | .priv_auto_alloc_size = sizeof(struct zynq_gem_priv), |
| 798 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 799 | }; |