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git01.mediatek.com / filogic / uboot / e32cce8680a8fc3aa472758e6c53470b72fea158 / . / arch / arm / mach-davinci / Kconfig
blob: 8fa2660a0cdcc786ea01ffb54d20adb0836ab28a [file] [log] [blame]
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]1if ARCH_DAVINCI
2
3choice
4 prompt "DaVinci board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]5 optional
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]6
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]7config TARGET_DA850EVM
8 bool "DA850 EVM board"
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]9 select MACH_DAVINCI_DA850_EVM
10 select SOC_DA850
Masahiro Yamada6e0971b2014-10-20 17:45:56 +0900[diff] [blame]11 select SUPPORT_SPL
Adam Ford389ee8d2024-05-01 04:57:50 -0500[diff] [blame]12 imply OF_UPSTREAM
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]13
Simon Glassa6664e92015-08-30 19:18:59 -0600[diff] [blame]14config TARGET_OMAPL138_LCDK
15 bool "OMAPL138 LCDK"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]16 select SOC_DA8XX
Simon Glassa6664e92015-08-30 19:18:59 -0600[diff] [blame]17 select SUPPORT_SPL
Bartosz Golaszewskif1412ef2019-11-14 16:10:30 +0100[diff] [blame]18 select SPL_BOARD_INIT
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]19
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]20config TARGET_LEGOEV3
21 bool "LEGO MINDSTORMS EV3"
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]22 select MACH_DAVINCI_DA850_EVM
23 select SOC_DA850
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]24
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]25endchoice
26
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]27config SYS_SOC
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]28 default "davinci"
29
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]30config DA850_LOWLEVEL
31 bool "Enable Lowlevel DA850 initialization"
32 depends on SOC_DA850
33
Fabien Parentb1bd48b2016-11-29 14:23:36 +0100[diff] [blame]34config SYS_DA850_PLL_INIT
35 bool
36
Fabien Parent06372b62016-11-29 14:23:37 +0100[diff] [blame]37config SYS_DA850_DDR_INIT
38 bool
39
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]40config SOC_DA850
41 bool
42 select SOC_DA8XX
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]43
44config SOC_DA8XX
45 bool
Lokesh Vutlabcb8d282018-03-16 14:22:12 +0530[diff] [blame]46 select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]47 select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL
Adam Fordd1f15a12018-01-11 08:20:27 -0600[diff] [blame]48
49config MACH_DAVINCI_DA850_EVM
50 bool
51
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]52if SYS_DA850_PLL_INIT
53comment "DA850 PLL Initialization Parameters"
54
55config SYS_DV_CLKMODE
56 int "PLLCTL Clock Mode"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]57 default 0
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]58 help
59 Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
60
61config SYS_DA850_PLL0_POSTDIV
62 int "PLLC0 PLL Post-Divider"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]63 default 1
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]64 help
65 Value written to PLLC0 PLL Post-Divider Control Register
66
67config SYS_DA850_PLL0_PLLDIV1
68 hex "PLLC0 Divider 1"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]69 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]70 help
71 Value written to PLLC0 Divider 1 register
72
73config SYS_DA850_PLL0_PLLDIV2
74 hex "PLLC0 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]75 default 0x8001
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]76 help
77 Value written to PLLC0 Divider 2 register
78
79config SYS_DA850_PLL0_PLLDIV3
80 hex "PLLC0 Divider 3"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]81 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]82 help
83 Value written to PLLC0 Divider 3 register
84
85config SYS_DA850_PLL0_PLLDIV4
86 hex "PLLC0 Divider 4"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]87 default 0x8003
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]88 help
89 Value written to PLLC0 Divider 4 register
90
91config SYS_DA850_PLL0_PLLDIV5
92 hex "PLLC0 Divider 5"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]93 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]94 help
95 Value written to PLLC0 Divider 5 register
96
97config SYS_DA850_PLL0_PLLDIV6
98 hex "PLLC0 Divider 6"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]99 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]100 help
101 Value written to PLLC0 Divider 6 register
102
103config SYS_DA850_PLL0_PLLDIV7
104 hex "PLLC0 Divider 7"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]105 default 0x8005
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]106 help
107 Value written to PLLC0 Divider 7 register
108
109config SYS_DA850_PLL1_POSTDIV
110 hex "PLLC1 PLL Post-Divider"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]111 default 1
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]112 help
113 Value written to PLLC1 PLL Post-Divider Control Register
114
115config SYS_DA850_PLL1_PLLDIV1
116 hex "PLLC1 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]117 default 0x8000
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]118 help
119 Value written to PLLC1 Divider 1 register
120
121config SYS_DA850_PLL1_PLLDIV2
122 hex "PLLC1 Divider 2"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]123 default 0x8001
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]124 help
125 Value written to PLLC1 Divider 2 register
126
127config SYS_DA850_PLL1_PLLDIV3
128 hex "PLLC1 Divider 3"
Tom Rinid97ca592018-01-31 15:34:49 -0500[diff] [blame]129 default 0x8002
Adam Ford71750ee2018-01-23 04:04:28 -0600[diff] [blame]130 help
131 Value written to PLLC1 Divider 3 register
132
133endif
134
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]135source "board/davinci/da8xxevm/Kconfig"
David Lechnera67f16f2016-02-26 00:46:07 -0600[diff] [blame]136source "board/lego/ev3/Kconfig"
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]137
Masahiro Yamadae604ef92014-08-31 07:11:01 +0900[diff] [blame]138endif