Blame - arch/arm/mach-davinci/Kconfig - filogic/uboot

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Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	1	if ARCH_DAVINCI
				2
				3	choice
				4	prompt "DaVinci board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	5	optional
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	6
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	7	config TARGET_IPAM390
				8	bool "IPAM390 board"
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	9	select MACH_DAVINCI_DA850_EVM
				10	select SOC_DA850
Masahiro Yamada	6e0971b	2014-10-20 17:45:56 +0900	[diff] [blame]	11	select SUPPORT_SPL
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	12
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	13	config TARGET_DA850EVM
				14	bool "DA850 EVM board"
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	15	select MACH_DAVINCI_DA850_EVM
				16	select SOC_DA850
Masahiro Yamada	6e0971b	2014-10-20 17:45:56 +0900	[diff] [blame]	17	select SUPPORT_SPL
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	18
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	19	config TARGET_EA20
				20	bool "EA20 board"
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	21	select MACH_DAVINCI_DA850_EVM
				22	select SOC_DA850
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	23	select BOARD_LATE_INIT
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	24
Simon Glass	a6664e9	2015-08-30 19:18:59 -0600	[diff] [blame]	25	config TARGET_OMAPL138_LCDK
				26	bool "OMAPL138 LCDK"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	27	select SOC_DA8XX
Simon Glass	a6664e9	2015-08-30 19:18:59 -0600	[diff] [blame]	28	select SUPPORT_SPL
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	29
				30	config TARGET_CALIMAIN
				31	bool "Calimain board"
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	32	select SOC_DA850
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	33
David Lechner	a67f16f	2016-02-26 00:46:07 -0600	[diff] [blame]	34	config TARGET_LEGOEV3
				35	bool "LEGO MINDSTORMS EV3"
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	36	select MACH_DAVINCI_DA850_EVM
				37	select SOC_DA850
David Lechner	a67f16f	2016-02-26 00:46:07 -0600	[diff] [blame]	38
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	39	endchoice
				40
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	41	config SYS_SOC
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	42	default "davinci"
				43
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	44	config DA850_LOWLEVEL
				45	bool "Enable Lowlevel DA850 initialization"
				46	depends on SOC_DA850
				47
Fabien Parent	b1bd48b	2016-11-29 14:23:36 +0100	[diff] [blame]	48	config SYS_DA850_PLL_INIT
				49	bool
				50
Fabien Parent	06372b6	2016-11-29 14:23:37 +0100	[diff] [blame]	51	config SYS_DA850_DDR_INIT
				52	bool
				53
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	54	config SOC_DA850
				55	bool
				56	select SOC_DA8XX
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	57
				58	config SOC_DA8XX
				59	bool
				60	select SYS_DA850_PLL_INIT if SUPPORT_SPL \|\| DA850_LOWLEVEL
Lokesh Vutla	bcb8d28	2018-03-16 14:22:12 +0530	[diff] [blame^]	61	select SYS_DA850_DDR_INIT if SUPPORT_SPL \|\| DA850_LOWLEVEL
Adam Ford	d1f15a1	2018-01-11 08:20:27 -0600	[diff] [blame]	62
				63	config MACH_DAVINCI_DA850_EVM
				64	bool
				65
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	66	if SYS_DA850_PLL_INIT
				67	comment "DA850 PLL Initialization Parameters"
				68
				69	config SYS_DV_CLKMODE
				70	int "PLLCTL Clock Mode"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	71	default 0
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	72	help
				73	Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
				74
				75	config SYS_DA850_PLL0_POSTDIV
				76	int "PLLC0 PLL Post-Divider"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	77	default 1
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	78	help
				79	Value written to PLLC0 PLL Post-Divider Control Register
				80
				81	config SYS_DA850_PLL0_PLLDIV1
				82	hex "PLLC0 Divider 1"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	83	default 0x8000
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	84	help
				85	Value written to PLLC0 Divider 1 register
				86
				87	config SYS_DA850_PLL0_PLLDIV2
				88	hex "PLLC0 Divider 2"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	89	default 0x8001
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	90	help
				91	Value written to PLLC0 Divider 2 register
				92
				93	config SYS_DA850_PLL0_PLLDIV3
				94	hex "PLLC0 Divider 3"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	95	default 0x8002
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	96	help
				97	Value written to PLLC0 Divider 3 register
				98
				99	config SYS_DA850_PLL0_PLLDIV4
				100	hex "PLLC0 Divider 4"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	101	default 0x8003
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	102	help
				103	Value written to PLLC0 Divider 4 register
				104
				105	config SYS_DA850_PLL0_PLLDIV5
				106	hex "PLLC0 Divider 5"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	107	default 0x8002
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	108	help
				109	Value written to PLLC0 Divider 5 register
				110
				111	config SYS_DA850_PLL0_PLLDIV6
				112	hex "PLLC0 Divider 6"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	113	default 0x8000
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	114	help
				115	Value written to PLLC0 Divider 6 register
				116
				117	config SYS_DA850_PLL0_PLLDIV7
				118	hex "PLLC0 Divider 7"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	119	default 0x8005
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	120	help
				121	Value written to PLLC0 Divider 7 register
				122
				123	config SYS_DA850_PLL1_POSTDIV
				124	hex "PLLC1 PLL Post-Divider"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	125	default 1
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	126	help
				127	Value written to PLLC1 PLL Post-Divider Control Register
				128
				129	config SYS_DA850_PLL1_PLLDIV1
				130	hex "PLLC1 Divider 2"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	131	default 0x8000
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	132	help
				133	Value written to PLLC1 Divider 1 register
				134
				135	config SYS_DA850_PLL1_PLLDIV2
				136	hex "PLLC1 Divider 2"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	137	default 0x8001
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	138	help
				139	Value written to PLLC1 Divider 2 register
				140
				141	config SYS_DA850_PLL1_PLLDIV3
				142	hex "PLLC1 Divider 3"
Tom Rini	d97ca59	2018-01-31 15:34:49 -0500	[diff] [blame]	143	default 0x8002
Adam Ford	71750ee	2018-01-23 04:04:28 -0600	[diff] [blame]	144	help
				145	Value written to PLLC1 Divider 3 register
				146
				147	endif
				148
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	149	source "board/Barix/ipam390/Kconfig"
				150	source "board/davinci/da8xxevm/Kconfig"
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	151	source "board/davinci/ea20/Kconfig"
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	152	source "board/omicron/calimain/Kconfig"
David Lechner	a67f16f	2016-02-26 00:46:07 -0600	[diff] [blame]	153	source "board/lego/ev3/Kconfig"
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	154
Philipp Tomsich	2d6a0cc	2017-08-03 23:23:55 +0200	[diff] [blame]	155	config SPL_LDSCRIPT
				156	default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390
				157	default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
				158
Masahiro Yamada	e604ef9	2014-08-31 07:11:01 +0900	[diff] [blame]	159	endif