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git01.mediatek.com / filogic / uboot / e32b06659e3588ff3eec7578b86bb1f0ac4e18c0 / . / arch / arm / dts / armada-38x-controlcenterdc.dts
blob: 79ea6f09095886976b4a9da9a0093ea0c3f6783f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]2/*
3 * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
4 *
5 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
6 *
7 * based on the Device Tree file for Marvell Armada 388 evaluation board
8 * (DB-88F6820), which is
9 *
10 * Copyright (C) 2014 Marvell
11 *
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]13 */
14
15/dts-v1/;
16
17#include "armada-388.dtsi"
18
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]19/ {
20 model = "Controlcenter Digital Compact";
21 compatible = "marvell,a385-db", "marvell,armada388",
22 "marvell,armada385", "marvell,armada380";
23
24 chosen {
25 bootargs = "console=ttyS1,115200 earlyprintk";
26 stdout-path = "/soc/internal-regs/serial@12100";
27 };
28
29 aliases {
30 ethernet0 = &eth0;
31 ethernet2 = &eth2;
32 mdio-gpio0 = &MDIO0;
33 mdio-gpio1 = &MDIO1;
34 mdio-gpio2 = &MDIO2;
35 spi0 = &spi0;
36 spi1 = &spi1;
37 i2c0 = &I2C0;
38 i2c1 = &I2C1;
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x10000000>; /* 256 MB */
44 };
45
46 clocks {
47 sc16isclk: sc16isclk {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <11059200>;
51 };
52 };
53
54 soc {
55 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
56 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
57
58 internal-regs {
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]59 I2C0: i2c@11000 {
60 status = "okay";
61 clock-frequency = <1000000>;
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]62 PCA21: pca9698@21 {
63 compatible = "nxp,pca9698";
64 reg = <0x21>;
65 #gpio-cells = <2>;
66 gpio-controller;
67 };
68 PCA22: pca9698@22 {
69 compatible = "nxp,pca9698";
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]70 reg = <0x22>;
71 #gpio-cells = <2>;
72 gpio-controller;
73 };
74 PCA23: pca9698@23 {
75 compatible = "nxp,pca9698";
76 reg = <0x23>;
77 #gpio-cells = <2>;
78 gpio-controller;
79 };
80 PCA24: pca9698@24 {
81 compatible = "nxp,pca9698";
82 reg = <0x24>;
83 #gpio-cells = <2>;
84 gpio-controller;
85 };
86 PCA25: pca9698@25 {
87 compatible = "nxp,pca9698";
88 reg = <0x25>;
89 #gpio-cells = <2>;
90 gpio-controller;
91 };
92 PCA26: pca9698@26 {
93 compatible = "nxp,pca9698";
94 reg = <0x26>;
95 #gpio-cells = <2>;
96 gpio-controller;
97 };
98 };
99
100 I2C1: i2c@11100 {
101 status = "okay";
102 clock-frequency = <400000>;
103 at97sc3205t@29 {
104 compatible = "atmel,at97sc3204t";
105 reg = <0x29>;
106 u-boot,i2c-offset-len = <0>;
107 };
108 emc2305@2d {
109 compatible = "smsc,emc2305";
110 #address-cells = <1>;
111 #size-cells = <0>;
112 reg = <0x2d>;
113 fan@0 {
114 reg = <0>;
115 };
116 fan@1 {
117 reg = <1>;
118 };
119 fan@2 {
120 reg = <2>;
121 };
122 fan@3 {
123 reg = <3>;
124 };
125 fan@4 {
126 reg = <4>;
127 };
128 };
129 lm77@48 {
130 compatible = "national,lm77";
131 reg = <0x48>;
132 };
133 ads1015@49 {
134 compatible = "ti,ads1015";
135 reg = <0x49>;
136 };
137 lm77@4a {
138 compatible = "national,lm77";
139 reg = <0x4a>;
140 };
141 ads1015@4b {
142 compatible = "ti,ads1015";
143 reg = <0x4b>;
144 };
145 emc2305@4c {
146 compatible = "smsc,emc2305";
147 #address-cells = <1>;
148 #size-cells = <0>;
149 reg = <0x4c>;
150 fan@0 {
151 reg = <0>;
152 };
153 fan@1 {
154 reg = <1>;
155 };
156 fan@2 {
157 reg = <2>;
158 };
159 fan@3 {
160 reg = <3>;
161 };
162 fan@4 {
163 reg = <4>;
164 };
165 };
166 at24c512@54 {
167 compatible = "atmel,24c512";
168 reg = <0x54>;
169 u-boot,i2c-offset-len = <2>;
170 };
171 ds1339@68 {
172 compatible = "dallas,ds1339";
173 reg = <0x68>;
174 };
175 };
176
177 serial@12000 {
178 status = "okay";
179 };
180
181 serial@12100 {
182 status = "okay";
183 };
184
185 ethernet@34000 {
186 status = "okay";
187 phy = <&phy1>;
188 phy-mode = "sgmii";
189 };
190
191 usb@58000 {
192 status = "ok";
193 };
194
195 ethernet@70000 {
196 status = "okay";
197 phy = <&phy0>;
198 phy-mode = "sgmii";
199 };
200
201 mdio@72004 {
202 phy0: ethernet-phy@0 {
203 reg = <1>;
204 };
205
206 phy1: ethernet-phy@1 {
207 reg = <0>;
208 };
209 };
210
211 sata@a8000 {
212 status = "okay";
213 };
214
215 sdhci@d8000 {
216 broken-cd;
217 wp-inverted;
218 bus-width = <4>;
219 status = "okay";
220 no-1-8-v;
221 };
222
223 usb3@f0000 {
224 status = "okay";
225 };
226 };
227
Chris Packham852a0e17c2019-03-16 20:46:20 +1300[diff] [blame]228 pcie {
Dirk Eibachfb605942017-02-22 16:07:23 +0100[diff] [blame]229 status = "okay";
230 /*
231 * The two PCIe units are accessible through
232 * standard PCIe slots on the board.
233 */
234 pcie@3,0 {
235 /* Port 0, Lane 0 */
236 status = "okay";
237 };
238 };
239
240 MDIO0: mdio0 {
241 compatible = "virtual,mdio-gpio";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 gpios = < /*MDC*/ &gpio0 13 0
245 /*MDIO*/ &gpio0 14 0>;
246 mv88e1240@0 {
247 reg = <0x0>;
248 };
249 mv88e1240@1 {
250 reg = <0x1>;
251 };
252 mv88e1240@2 {
253 reg = <0x2>;
254 };
255 mv88e1240@3 {
256 reg = <0x3>;
257 };
258 mv88e1240@4 {
259 reg = <0x4>;
260 };
261 mv88e1240@5 {
262 reg = <0x5>;
263 };
264 mv88e1240@6 {
265 reg = <0x6>;
266 };
267 mv88e1240@7 {
268 reg = <0x7>;
269 };
270 mv88e1240@8 {
271 reg = <0x8>;
272 };
273 mv88e1240@9 {
274 reg = <0x9>;
275 };
276 mv88e1240@a {
277 reg = <0xa>;
278 };
279 mv88e1240@b {
280 reg = <0xb>;
281 };
282 mv88e1240@c {
283 reg = <0xc>;
284 };
285 mv88e1240@d {
286 reg = <0xd>;
287 };
288 mv88e1240@e {
289 reg = <0xe>;
290 };
291 mv88e1240@f {
292 reg = <0xf>;
293 };
294 mv88e1240@10 {
295 reg = <0x10>;
296 };
297 mv88e1240@11 {
298 reg = <0x11>;
299 };
300 mv88e1240@12 {
301 reg = <0x12>;
302 };
303 mv88e1240@13 {
304 reg = <0x13>;
305 };
306 mv88e1240@14 {
307 reg = <0x14>;
308 };
309 mv88e1240@15 {
310 reg = <0x15>;
311 };
312 mv88e1240@16 {
313 reg = <0x16>;
314 };
315 mv88e1240@17 {
316 reg = <0x17>;
317 };
318 mv88e1240@18 {
319 reg = <0x18>;
320 };
321 mv88e1240@19 {
322 reg = <0x19>;
323 };
324 mv88e1240@1a {
325 reg = <0x1a>;
326 };
327 mv88e1240@1b {
328 reg = <0x1b>;
329 };
330 mv88e1240@1c {
331 reg = <0x1c>;
332 };
333 mv88e1240@1d {
334 reg = <0x1d>;
335 };
336 mv88e1240@1e {
337 reg = <0x1e>;
338 };
339 mv88e1240@1f {
340 reg = <0x1f>;
341 };
342 };
343
344 MDIO1: mdio1 {
345 compatible = "virtual,mdio-gpio";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 gpios = < /*MDC*/ &gpio0 25 0
349 /*MDIO*/ &gpio1 13 0>;
350 mv88e1240@0 {
351 reg = <0x0>;
352 };
353 mv88e1240@1 {
354 reg = <0x1>;
355 };
356 mv88e1240@2 {
357 reg = <0x2>;
358 };
359 mv88e1240@3 {
360 reg = <0x3>;
361 };
362 mv88e1240@4 {
363 reg = <0x4>;
364 };
365 mv88e1240@5 {
366 reg = <0x5>;
367 };
368 mv88e1240@6 {
369 reg = <0x6>;
370 };
371 mv88e1240@7 {
372 reg = <0x7>;
373 };
374 mv88e1240@8 {
375 reg = <0x8>;
376 };
377 mv88e1240@9 {
378 reg = <0x9>;
379 };
380 mv88e1240@a {
381 reg = <0xa>;
382 };
383 mv88e1240@b {
384 reg = <0xb>;
385 };
386 mv88e1240@c {
387 reg = <0xc>;
388 };
389 mv88e1240@d {
390 reg = <0xd>;
391 };
392 mv88e1240@e {
393 reg = <0xe>;
394 };
395 mv88e1240@f {
396 reg = <0xf>;
397 };
398 mv88e1240@10 {
399 reg = <0x10>;
400 };
401 mv88e1240@11 {
402 reg = <0x11>;
403 };
404 mv88e1240@12 {
405 reg = <0x12>;
406 };
407 mv88e1240@13 {
408 reg = <0x13>;
409 };
410 mv88e1240@14 {
411 reg = <0x14>;
412 };
413 mv88e1240@15 {
414 reg = <0x15>;
415 };
416 mv88e1240@16 {
417 reg = <0x16>;
418 };
419 mv88e1240@17 {
420 reg = <0x17>;
421 };
422 mv88e1240@18 {
423 reg = <0x18>;
424 };
425 mv88e1240@19 {
426 reg = <0x19>;
427 };
428 mv88e1240@1a {
429 reg = <0x1a>;
430 };
431 mv88e1240@1b {
432 reg = <0x1b>;
433 };
434 mv88e1240@1c {
435 reg = <0x1c>;
436 };
437 mv88e1240@1d {
438 reg = <0x1d>;
439 };
440 mv88e1240@1e {
441 reg = <0x1e>;
442 };
443 mv88e1240@1f {
444 reg = <0x1f>;
445 };
446 };
447
448 MDIO2: mdio2 {
449 compatible = "virtual,mdio-gpio";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 gpios = < /*MDC*/ &gpio1 14 0
453 /*MDIO*/ &gpio0 24 0>;
454 mv88e1240@0 {
455 reg = <0x0>;
456 };
457 mv88e1240@1 {
458 reg = <0x1>;
459 };
460 mv88e1240@2 {
461 reg = <0x2>;
462 };
463 mv88e1240@3 {
464 reg = <0x3>;
465 };
466 mv88e1240@4 {
467 reg = <0x4>;
468 };
469 mv88e1240@5 {
470 reg = <0x5>;
471 };
472 mv88e1240@6 {
473 reg = <0x6>;
474 };
475 mv88e1240@7 {
476 reg = <0x7>;
477 };
478 mv88e1240@8 {
479 reg = <0x8>;
480 };
481 mv88e1240@9 {
482 reg = <0x9>;
483 };
484 mv88e1240@a {
485 reg = <0xa>;
486 };
487 mv88e1240@b {
488 reg = <0xb>;
489 };
490 mv88e1240@c {
491 reg = <0xc>;
492 };
493 mv88e1240@d {
494 reg = <0xd>;
495 };
496 mv88e1240@e {
497 reg = <0xe>;
498 };
499 mv88e1240@f {
500 reg = <0xf>;
501 };
502 mv88e1240@10 {
503 reg = <0x10>;
504 };
505 mv88e1240@11 {
506 reg = <0x11>;
507 };
508 mv88e1240@12 {
509 reg = <0x12>;
510 };
511 mv88e1240@13 {
512 reg = <0x13>;
513 };
514 mv88e1240@14 {
515 reg = <0x14>;
516 };
517 mv88e1240@15 {
518 reg = <0x15>;
519 };
520 };
521 };
522
523 leds {
524 compatible = "gpio-leds";
525
526 finder_led {
527 label = "finder-led";
528 gpios = <&PCA22 25 0>;
529 };
530
531 status_led {
532 label = "status-led";
533 gpios = <&gpio0 29 0>;
534 };
535 };
536};
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]537
538&spi0 {
539 status = "okay";
540 sc16is741: sc16is741@0 {
541 compatible = "nxp,sc16is741";
542 reg = <0>;
543 clocks = <&sc16isclk>;
544 spi-max-frequency = <4000000>;
545 interrupt-parent = <&gpio0>;
546 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
547 gpio-controller;
548 #gpio-cells = <2>;
549 };
550};
551
552&spi1 {
553 status = "okay";
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]554 spi-flash@0 {
555 #address-cells = <1>;
556 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]557 compatible = "n25q016a", "jedec,spi-nor";
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]558 reg = <0>; /* Chip select 0 */
559 spi-max-frequency = <108000000>;
560 };
561 spi-flash@1 {
562 #address-cells = <1>;
563 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000[diff] [blame]564 compatible = "n25q128a11", "jedec,spi-nor";
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]565 reg = <1>; /* Chip select 1 */
566 spi-max-frequency = <108000000>;
Chris Packham06db9d22018-12-10 20:07:51 +1300[diff] [blame]567 };
568};