blob: 826dc5148661da3e9a146b93b408a8a047b15f02 [file] [log] [blame]
Ramon Friede43d8e72018-05-16 12:13:40 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TLMM driver for Qualcomm APQ8016, APQ8096
4 *
5 * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
6 *
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <asm/io.h>
Sumit Gargb7572e52022-07-27 13:52:04 +053013#include <dm/device_compat.h>
14#include <dm/lists.h>
Ramon Friede43d8e72018-05-16 12:13:40 +030015#include <dm/pinctrl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Ramon Friede43d8e72018-05-16 12:13:40 +030017#include "pinctrl-snapdragon.h"
18
19struct msm_pinctrl_priv {
20 phys_addr_t base;
21 struct msm_pinctrl_data *data;
22};
23
24#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
25#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
26#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
27#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
Ramon Fried772a99a2019-01-12 11:47:27 +020028#define TLMM_GPIO_DISABLE BIT(9)
Ramon Friede43d8e72018-05-16 12:13:40 +030029
30static const struct pinconf_param msm_conf_params[] = {
Sumit Gargfd1ad932023-02-01 19:28:52 +053031 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
Ramon Friede43d8e72018-05-16 12:13:40 +030032 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
Sumit Gargfd1ad932023-02-01 19:28:52 +053033 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
Ramon Friede43d8e72018-05-16 12:13:40 +030034};
35
36static int msm_get_functions_count(struct udevice *dev)
37{
38 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
39
40 return priv->data->functions_count;
41}
42
43static int msm_get_pins_count(struct udevice *dev)
44{
45 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
46
47 return priv->data->pin_count;
48}
49
50static const char *msm_get_function_name(struct udevice *dev,
51 unsigned int selector)
52{
53 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
54
55 return priv->data->get_function_name(dev, selector);
56}
57
58static int msm_pinctrl_probe(struct udevice *dev)
59{
60 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
61
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +090062 priv->base = dev_read_addr(dev);
Ramon Friede43d8e72018-05-16 12:13:40 +030063 priv->data = (struct msm_pinctrl_data *)dev->driver_data;
64
65 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
66}
67
68static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
69{
70 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
71
72 return priv->data->get_pin_name(dev, selector);
73}
74
75static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
76 unsigned int func_selector)
77{
78 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
79
80 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
Ramon Fried772a99a2019-01-12 11:47:27 +020081 TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
Ramon Friede43d8e72018-05-16 12:13:40 +030082 priv->data->get_function_mux(func_selector) << 2);
83 return 0;
84}
85
86static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
87 unsigned int param, unsigned int argument)
88{
89 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
90
91 switch (param) {
92 case PIN_CONFIG_DRIVE_STRENGTH:
Sumit Gargfd1ad932023-02-01 19:28:52 +053093 argument = (argument / 2) - 1;
Ramon Friede43d8e72018-05-16 12:13:40 +030094 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
95 TLMM_DRV_STRENGTH_MASK, argument << 6);
96 break;
97 case PIN_CONFIG_BIAS_DISABLE:
98 clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
99 TLMM_GPIO_PULL_MASK);
100 break;
Sumit Gargfd1ad932023-02-01 19:28:52 +0530101 case PIN_CONFIG_BIAS_PULL_UP:
102 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
103 TLMM_GPIO_PULL_MASK, argument);
104 break;
Ramon Friede43d8e72018-05-16 12:13:40 +0300105 default:
106 return 0;
107 }
108
109 return 0;
110}
111
112static struct pinctrl_ops msm_pinctrl_ops = {
113 .get_pins_count = msm_get_pins_count,
114 .get_pin_name = msm_get_pin_name,
115 .set_state = pinctrl_generic_set_state,
116 .pinmux_set = msm_pinmux_set,
117 .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
118 .pinconf_params = msm_conf_params,
119 .pinconf_set = msm_pinconf_set,
120 .get_functions_count = msm_get_functions_count,
121 .get_function_name = msm_get_function_name,
122};
123
Sumit Gargb7572e52022-07-27 13:52:04 +0530124static int msm_pinctrl_bind(struct udevice *dev)
125{
126 ofnode node = dev_ofnode(dev);
127 const char *name;
128 int ret;
129
130 ofnode_get_property(node, "gpio-controller", &ret);
131 if (ret < 0)
132 return 0;
133
134 /* Get the name of gpio node */
135 name = ofnode_get_name(node);
136 if (!name)
137 return -EINVAL;
138
139 /* Bind gpio node */
140 ret = device_bind_driver_to_node(dev, "gpio_msm",
141 name, node, NULL);
142 if (ret)
143 return ret;
144
145 dev_dbg(dev, "bind %s\n", name);
146
147 return 0;
148}
149
Ramon Friede43d8e72018-05-16 12:13:40 +0300150static const struct udevice_id msm_pinctrl_ids[] = {
Sumit Gargb7572e52022-07-27 13:52:04 +0530151 { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
152 { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
153 { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
154 { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
Ramon Friede43d8e72018-05-16 12:13:40 +0300155 { }
156};
157
158U_BOOT_DRIVER(pinctrl_snapdraon) = {
159 .name = "pinctrl_msm",
160 .id = UCLASS_PINCTRL,
161 .of_match = msm_pinctrl_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700162 .priv_auto = sizeof(struct msm_pinctrl_priv),
Ramon Friede43d8e72018-05-16 12:13:40 +0300163 .ops = &msm_pinctrl_ops,
164 .probe = msm_pinctrl_probe,
Sumit Gargb7572e52022-07-27 13:52:04 +0530165 .bind = msm_pinctrl_bind,
Ramon Friede43d8e72018-05-16 12:13:40 +0300166};