blob: ab884ab6bf9a86b141ac3cc028825f5a0000dbdc [file] [log] [blame]
Ramon Friede43d8e72018-05-16 12:13:40 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * TLMM driver for Qualcomm APQ8016, APQ8096
4 *
5 * (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
6 *
7 */
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <asm/io.h>
Sumit Gargb7572e52022-07-27 13:52:04 +053013#include <dm/device_compat.h>
14#include <dm/lists.h>
Ramon Friede43d8e72018-05-16 12:13:40 +030015#include <dm/pinctrl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060016#include <linux/bitops.h>
Ramon Friede43d8e72018-05-16 12:13:40 +030017#include "pinctrl-snapdragon.h"
18
19struct msm_pinctrl_priv {
20 phys_addr_t base;
21 struct msm_pinctrl_data *data;
22};
23
24#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000)
25#define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
26#define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
27#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
Ramon Fried772a99a2019-01-12 11:47:27 +020028#define TLMM_GPIO_DISABLE BIT(9)
Ramon Friede43d8e72018-05-16 12:13:40 +030029
30static const struct pinconf_param msm_conf_params[] = {
31 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
32 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
33};
34
35static int msm_get_functions_count(struct udevice *dev)
36{
37 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
38
39 return priv->data->functions_count;
40}
41
42static int msm_get_pins_count(struct udevice *dev)
43{
44 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
45
46 return priv->data->pin_count;
47}
48
49static const char *msm_get_function_name(struct udevice *dev,
50 unsigned int selector)
51{
52 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
53
54 return priv->data->get_function_name(dev, selector);
55}
56
57static int msm_pinctrl_probe(struct udevice *dev)
58{
59 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
60
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +090061 priv->base = dev_read_addr(dev);
Ramon Friede43d8e72018-05-16 12:13:40 +030062 priv->data = (struct msm_pinctrl_data *)dev->driver_data;
63
64 return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
65}
66
67static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector)
68{
69 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
70
71 return priv->data->get_pin_name(dev, selector);
72}
73
74static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
75 unsigned int func_selector)
76{
77 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
78
79 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
Ramon Fried772a99a2019-01-12 11:47:27 +020080 TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
Ramon Friede43d8e72018-05-16 12:13:40 +030081 priv->data->get_function_mux(func_selector) << 2);
82 return 0;
83}
84
85static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
86 unsigned int param, unsigned int argument)
87{
88 struct msm_pinctrl_priv *priv = dev_get_priv(dev);
89
90 switch (param) {
91 case PIN_CONFIG_DRIVE_STRENGTH:
92 clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
93 TLMM_DRV_STRENGTH_MASK, argument << 6);
94 break;
95 case PIN_CONFIG_BIAS_DISABLE:
96 clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
97 TLMM_GPIO_PULL_MASK);
98 break;
99 default:
100 return 0;
101 }
102
103 return 0;
104}
105
106static struct pinctrl_ops msm_pinctrl_ops = {
107 .get_pins_count = msm_get_pins_count,
108 .get_pin_name = msm_get_pin_name,
109 .set_state = pinctrl_generic_set_state,
110 .pinmux_set = msm_pinmux_set,
111 .pinconf_num_params = ARRAY_SIZE(msm_conf_params),
112 .pinconf_params = msm_conf_params,
113 .pinconf_set = msm_pinconf_set,
114 .get_functions_count = msm_get_functions_count,
115 .get_function_name = msm_get_function_name,
116};
117
Sumit Gargb7572e52022-07-27 13:52:04 +0530118static int msm_pinctrl_bind(struct udevice *dev)
119{
120 ofnode node = dev_ofnode(dev);
121 const char *name;
122 int ret;
123
124 ofnode_get_property(node, "gpio-controller", &ret);
125 if (ret < 0)
126 return 0;
127
128 /* Get the name of gpio node */
129 name = ofnode_get_name(node);
130 if (!name)
131 return -EINVAL;
132
133 /* Bind gpio node */
134 ret = device_bind_driver_to_node(dev, "gpio_msm",
135 name, node, NULL);
136 if (ret)
137 return ret;
138
139 dev_dbg(dev, "bind %s\n", name);
140
141 return 0;
142}
143
Ramon Friede43d8e72018-05-16 12:13:40 +0300144static const struct udevice_id msm_pinctrl_ids[] = {
Sumit Gargb7572e52022-07-27 13:52:04 +0530145 { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
146 { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
147 { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
148 { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
Ramon Friede43d8e72018-05-16 12:13:40 +0300149 { }
150};
151
152U_BOOT_DRIVER(pinctrl_snapdraon) = {
153 .name = "pinctrl_msm",
154 .id = UCLASS_PINCTRL,
155 .of_match = msm_pinctrl_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700156 .priv_auto = sizeof(struct msm_pinctrl_priv),
Ramon Friede43d8e72018-05-16 12:13:40 +0300157 .ops = &msm_pinctrl_ops,
158 .probe = msm_pinctrl_probe,
Sumit Gargb7572e52022-07-27 13:52:04 +0530159 .bind = msm_pinctrl_bind,
Ramon Friede43d8e72018-05-16 12:13:40 +0300160};