blob: f8b4bf2df9b65c603c8d0dcb00c4b6e6eb40bc0b [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2022 Toradex
4 */
5
6#ifndef __VERDIN_IMX8MP_H
7#define __VERDIN_IMX8MP_H
8
9#include <asm/arch/imx-regs.h>
10#include <linux/sizes.h>
11
12#define CONFIG_SPL_MAX_SIZE (152 * 1024)
13#define CONFIG_SYS_MONITOR_LEN SZ_512K
14#define CONFIG_SYS_UBOOT_BASE \
15 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
16
17#ifdef CONFIG_SPL_BUILD
18/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
19#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
20#define CONFIG_SPL_STACK 0x960000
21#define CONFIG_SPL_BSS_START_ADDR 0x0098fc00
22#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
23#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
24#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
25
26/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
27#define CONFIG_MALLOC_F_ADDR 0x184000
28/* For RAW image gives a error info not panic */
29#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
30
31#define CONFIG_POWER_PCA9450
32
33#define CONFIG_SYS_I2C
34#define CONFIG_SYS_I2C_SPEED 100000
35#endif /* CONFIG_SPL_BUILD */
36
37#define CONFIG_REMAKE_ELF
38
39/* ENET Config */
40/* ENET1 */
41#if defined(CONFIG_CMD_NET)
42#define CONFIG_ETHPRIME "eth0" /* eqos is aliased on-module Ethernet interface */
43
44#define CONFIG_FEC_XCV_TYPE RGMII
45#define CONFIG_FEC_MXC_PHYADDR 7
46#define FEC_QUIRK_ENET_MAC
47
48#define PHY_ANEG_TIMEOUT 20000
49#endif /* CONFIG_CMD_NET */
50
51#define MEM_LAYOUT_ENV_SETTINGS \
52 "fdt_addr_r=0x43000000\0" \
53 "kernel_addr_r=0x40000000\0" \
54 "ramdisk_addr_r=0x46400000\0" \
55 "scriptaddr=0x46000000\0"
56
57/* Enable Distro Boot */
58#ifndef CONFIG_SPL_BUILD
59#define BOOT_TARGET_DEVICES(func) \
60 func(MMC, mmc, 1) \
61 func(MMC, mmc, 2) \
62 func(DHCP, dhcp, na)
63#include <config_distro_bootcmd.h>
64#undef CONFIG_ISO_PARTITION
65#else
66#define BOOTENV
67#endif
68
69#if defined(CONFIG_TDX_EASY_INSTALLER)
70# define BOOT_SCRIPT "boot-tezi.scr"
71#else
72# define BOOT_SCRIPT "boot.scr"
73#endif
74
75/* Initial environment variables */
76#define CONFIG_EXTRA_ENV_SETTINGS \
77 BOOTENV \
78 MEM_LAYOUT_ENV_SETTINGS \
79 "bootcmd_mfg=fastboot 0\0" \
80 "boot_file=Image\0" \
81 "boot_scripts=" BOOT_SCRIPT "\0" \
82 "boot_script_dhcp=" BOOT_SCRIPT "\0" \
83 "console=ttymxc2\0" \
84 "fdt_board=dev\0" \
85 "initrd_addr=0x43800000\0" \
86 "initrd_high=0xffffffffffffffff\0" \
87 "netargs=setenv bootargs console=${console},${baudrate} " \
88 "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
89 "\0" \
90 "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
91 "tftp ${fdt_addr} verdin/${fdtfile}; " \
92 "booti ${loadaddr} - ${fdt_addr}\0" \
93 "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \
94 "consoleblank=0 earlycon\0" \
95 "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
96 "if test \"$confirm\" = \"y\"; then " \
97 "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
98 "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
99 "${blkcnt}; fi\0"
100
101#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
102#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
103#define CONFIG_SYS_INIT_SP_OFFSET \
104 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
105#define CONFIG_SYS_INIT_SP_ADDR \
106 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
107
108#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */
109
110/* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
111#define CONFIG_SYS_SDRAM_BASE 0x40000000
112#define PHYS_SDRAM 0x40000000
113#define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
114#define PHYS_SDRAM_2 0x100000000
115#define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
116
117/* UART */
118#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
119
120/* Monitor Command Prompt */
121#define CONFIG_SYS_CBSIZE SZ_2K
122#define CONFIG_SYS_MAXARGS 64
123#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
125 sizeof(CONFIG_SYS_PROMPT) + 16)
126
127/* USDHC */
128#define CONFIG_SYS_FSL_USDHC_NUM 2
129#define CONFIG_SYS_FSL_ESDHC_ADDR 0
130
131#endif /* __VERDIN_IMX8MP_H */