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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bo Shen42aafb32012-07-05 17:21:46 +00002/*
3 * Copyright (C) 2012 Atmel Corporation
4 *
5 * Configuation settings for the AT91SAM9X5EK board.
Bo Shen42aafb32012-07-05 17:21:46 +00006 */
7
8#ifndef __CONFIG_H__
9#define __CONFIG_H__
10
Bo Shen42aafb32012-07-05 17:21:46 +000011/* ARM asynchronous clock */
12#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
13#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
Bo Shen42aafb32012-07-05 17:21:46 +000014
Bo Shen42aafb32012-07-05 17:21:46 +000015#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
16#define CONFIG_SETUP_MEMORY_TAGS
17#define CONFIG_INITRD_TAG
Bo Shen42aafb32012-07-05 17:21:46 +000018
19/* general purpose I/O */
20#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Bo Shen42aafb32012-07-05 17:21:46 +000021
Bo Shen42aafb32012-07-05 17:21:46 +000022/*
23 * BOOTP options
24 */
25#define CONFIG_BOOTP_BOOTFILESIZE
Bo Shen42aafb32012-07-05 17:21:46 +000026
27/*
Tom Riniceed5d22017-05-12 22:33:27 -040028 * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
Richard Genoud1e34e832012-11-29 23:18:34 +000029 * NB: in this case, USB 1.1 devices won't be recognized.
30 */
31
Bo Shen42aafb32012-07-05 17:21:46 +000032/* SDRAM */
Bo Shen42aafb32012-07-05 17:21:46 +000033#define CONFIG_SYS_SDRAM_BASE 0x20000000
34#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
35
36#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yangf345e282017-04-18 14:51:54 +080037 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shen42aafb32012-07-05 17:21:46 +000038
39/* DataFlash */
Bo Shen42aafb32012-07-05 17:21:46 +000040
Bo Shen42aafb32012-07-05 17:21:46 +000041/* NAND flash */
42#ifdef CONFIG_CMD_NAND
Bo Shen42aafb32012-07-05 17:21:46 +000043#define CONFIG_SYS_MAX_NAND_DEVICE 1
44#define CONFIG_SYS_NAND_BASE 0x40000000
45#define CONFIG_SYS_NAND_DBW_8 1
46/* our ALE is AD21 */
47#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
48/* our CLE is AD22 */
49#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
50#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
51#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
Tom Rini00448d22017-07-28 21:31:42 -040052#endif
53
Richard Genoud1e34e832012-11-29 23:18:34 +000054/* USB */
55#ifdef CONFIG_CMD_USB
Tom Riniceed5d22017-05-12 22:33:27 -040056#ifndef CONFIG_USB_EHCI_HCD
Bo Shen4a985df2013-10-21 16:14:00 +080057#define CONFIG_USB_ATMEL
58#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Richard Genoud1e34e832012-11-29 23:18:34 +000059#define CONFIG_USB_OHCI_NEW
60#define CONFIG_SYS_USB_OHCI_CPU_INIT
61#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
62#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5"
63#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
64#endif
Richard Genoud1e34e832012-11-29 23:18:34 +000065#endif
66
Wenyou Yange035ea72017-09-14 11:07:44 +080067#ifdef CONFIG_NAND_BOOT
Bo Shen42aafb32012-07-05 17:21:46 +000068/* bootstrap + u-boot + env + linux in nandflash */
Bo Shen42aafb32012-07-05 17:21:46 +000069#define CONFIG_BOOTCOMMAND "nand read " \
Eugen.Hristev@microchip.comdc9a4932018-10-23 07:41:33 +000070 "0x22000000 0x200000 0x600000; " \
71 "nand read 0x21000000 0x180000 0x20000; " \
72 "bootz 0x22000000 - 0x21000000"
Wenyou Yange035ea72017-09-14 11:07:44 +080073#elif defined(CONFIG_SPI_BOOT)
Bo Shen4a73e582012-08-19 20:32:24 +000074/* bootstrap + u-boot + env + linux in spi flash */
Bo Shen4a73e582012-08-19 20:32:24 +000075#define CONFIG_BOOTCOMMAND "sf probe 0; " \
76 "sf read 0x22000000 0x100000 0x300000; " \
77 "bootm 0x22000000"
Bo Shen0a9f8ac2012-12-06 21:37:04 +000078#elif defined(CONFIG_SYS_USE_DATAFLASH)
79/* bootstrap + u-boot + env + linux in data flash */
Bo Shen0a9f8ac2012-12-06 21:37:04 +000080#define CONFIG_BOOTCOMMAND "sf probe 0; " \
81 "sf read 0x22000000 0x84000 0x294000; " \
82 "bootm 0x22000000"
Bo Shen42aafb32012-07-05 17:21:46 +000083#endif
84
Bo Shen9a3b1fe2015-03-27 14:23:35 +080085/* SPL */
Bo Shen9a3b1fe2015-03-27 14:23:35 +080086#define CONFIG_SPL_MAX_SIZE 0x6000
87#define CONFIG_SPL_STACK 0x308000
88
89#define CONFIG_SPL_BSS_START_ADDR 0x20000000
90#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
91#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
92#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
93
Bo Shen9a3b1fe2015-03-27 14:23:35 +080094#define CONFIG_SYS_MONITOR_LEN (512 << 10)
95
96#define CONFIG_SYS_MASTER_CLOCK 132096000
97#define CONFIG_SYS_AT91_PLLA 0x20c73f03
98#define CONFIG_SYS_MCKR 0x1301
99#define CONFIG_SYS_MCKR_CSS 0x1302
100
Wenyou Yange035ea72017-09-14 11:07:44 +0800101#ifdef CONFIG_SD_BOOT
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800102#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Wenyou Yange035ea72017-09-14 11:07:44 +0800103#endif
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800104#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
105#define CONFIG_SYS_NAND_5_ADDR_CYCLE
106#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
107#define CONFIG_SYS_NAND_PAGE_COUNT 64
108#define CONFIG_SYS_NAND_OOBSIZE 64
109#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
110#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Bo Shen9a3b1fe2015-03-27 14:23:35 +0800111
Bo Shen42aafb32012-07-05 17:21:46 +0000112#endif