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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek15d654c2013-04-22 15:43:02 +02002/*
3 * (C) Copyright 2012-2013, Xilinx, Michal Simek
4 *
5 * (C) Copyright 2012
6 * Joe Hershberger <joe.hershberger@ni.com>
Michal Simek15d654c2013-04-22 15:43:02 +02007 */
8
9#ifndef _ZYNQPL_H_
10#define _ZYNQPL_H_
11
12#include <xilinx.h>
13
Siva Durga Prasad Paladugue4603522018-06-26 15:02:19 +053014#ifdef CONFIG_CMD_ZYNQ_AES
Siva Durga Prasad Paladuguc5750582015-12-09 18:46:43 +053015int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen,
16 u8 bstype);
Siva Durga Prasad Paladugue4603522018-06-26 15:02:19 +053017#endif
18
Michal Simek75fafac2014-03-13 13:07:57 +010019extern struct xilinx_fpga_op zynq_op;
Michal Simek15d654c2013-04-22 15:43:02 +020020
Michal Simekf31d90f2018-01-17 10:56:22 -030021#define XILINX_ZYNQ_XC7Z007S 0x3
22#define XILINX_ZYNQ_XC7Z010 0x2
Michal Simek47d40532024-07-30 15:50:17 +020023#define XILINX_ZYNQ_XC7Z010_LR 0x4
Michal Simekf31d90f2018-01-17 10:56:22 -030024#define XILINX_ZYNQ_XC7Z012S 0x1c
25#define XILINX_ZYNQ_XC7Z014S 0x8
26#define XILINX_ZYNQ_XC7Z015 0x1b
Michal Simek47d40532024-07-30 15:50:17 +020027#define XILINX_ZYNQ_XC7Z020_LR 0x9
Michal Simekf31d90f2018-01-17 10:56:22 -030028#define XILINX_ZYNQ_XC7Z020 0x7
29#define XILINX_ZYNQ_XC7Z030 0xc
30#define XILINX_ZYNQ_XC7Z035 0x12
31#define XILINX_ZYNQ_XC7Z045 0x11
32#define XILINX_ZYNQ_XC7Z100 0x16
Michal Simek15d654c2013-04-22 15:43:02 +020033
34/* Device Image Sizes */
Michal Simek82c97022016-10-18 16:10:25 +020035#define XILINX_XC7Z007S_SIZE 16669920/8
Michal Simek15d654c2013-04-22 15:43:02 +020036#define XILINX_XC7Z010_SIZE 16669920/8
Michal Simek47d40532024-07-30 15:50:17 +020037#define XILINX_XC7Z010_LR_SIZE 16669920/8
Michal Simek82c97022016-10-18 16:10:25 +020038#define XILINX_XC7Z012S_SIZE 28085344/8
39#define XILINX_XC7Z014S_SIZE 32364512/8
Michal Simek0e91d3a2013-09-26 16:39:03 +020040#define XILINX_XC7Z015_SIZE 28085344/8
Michal Simek47d40532024-07-30 15:50:17 +020041#define XILINX_XC7Z020_LR_SIZE 32364512/8
Michal Simek15d654c2013-04-22 15:43:02 +020042#define XILINX_XC7Z020_SIZE 32364512/8
43#define XILINX_XC7Z030_SIZE 47839328/8
Siva Durga Prasad Paladugu77fc12c2014-11-25 15:29:54 +053044#define XILINX_XC7Z035_SIZE 106571232/8
Michal Simek15d654c2013-04-22 15:43:02 +020045#define XILINX_XC7Z045_SIZE 106571232/8
Michal Simek52f91b52013-06-17 13:54:07 +020046#define XILINX_XC7Z100_SIZE 139330784/8
Michal Simek15d654c2013-04-22 15:43:02 +020047
Michal Simekf31d90f2018-01-17 10:56:22 -030048/* Device Names */
49#define XILINX_XC7Z007S_NAME "7z007s"
50#define XILINX_XC7Z010_NAME "7z010"
Michal Simek47d40532024-07-30 15:50:17 +020051#define XILINX_XC7Z010_LR_NAME "xc7z010_lr"
Michal Simekf31d90f2018-01-17 10:56:22 -030052#define XILINX_XC7Z012S_NAME "7z012s"
53#define XILINX_XC7Z014S_NAME "7z014s"
54#define XILINX_XC7Z015_NAME "7z015"
Michal Simek47d40532024-07-30 15:50:17 +020055#define XILINX_XC7Z020_LR_NAME "xa7z020_lr"
Michal Simekf31d90f2018-01-17 10:56:22 -030056#define XILINX_XC7Z020_NAME "7z020"
57#define XILINX_XC7Z030_NAME "7z030"
58#define XILINX_XC7Z035_NAME "7z035"
59#define XILINX_XC7Z045_NAME "7z045"
60#define XILINX_XC7Z100_NAME "7z100"
Michal Simek0e91d3a2013-09-26 16:39:03 +020061
Michal Simekf31d90f2018-01-17 10:56:22 -030062#if defined(CONFIG_FPGA)
63#define ZYNQ_DESC(name) { \
64 .idcode = XILINX_ZYNQ_XC##name, \
65 .fpga_size = XILINX_XC##name##_SIZE, \
66 .devicename = XILINX_XC##name##_NAME \
67 }
68#else
69#define ZYNQ_DESC(name) { \
70 .idcode = XILINX_ZYNQ_XC##name, \
71 .devicename = XILINX_XC##name##_NAME \
72 }
73#endif
Michal Simek52f91b52013-06-17 13:54:07 +020074
Michal Simek15d654c2013-04-22 15:43:02 +020075#endif /* _ZYNQPL_H_ */