ARM: zynq: Add support for 7z010_lr and 7z020_lr
Add support for *_lr SOCs. Without this change chips are not going to be
properly identified and bitstream programming won't work.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/14d8905a89d1b31fbb2318512cf57eb0256c11be.1722347416.git.michal.simek@amd.com
diff --git a/include/zynqpl.h b/include/zynqpl.h
index d7dc064..08d067d 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -20,9 +20,11 @@
#define XILINX_ZYNQ_XC7Z007S 0x3
#define XILINX_ZYNQ_XC7Z010 0x2
+#define XILINX_ZYNQ_XC7Z010_LR 0x4
#define XILINX_ZYNQ_XC7Z012S 0x1c
#define XILINX_ZYNQ_XC7Z014S 0x8
#define XILINX_ZYNQ_XC7Z015 0x1b
+#define XILINX_ZYNQ_XC7Z020_LR 0x9
#define XILINX_ZYNQ_XC7Z020 0x7
#define XILINX_ZYNQ_XC7Z030 0xc
#define XILINX_ZYNQ_XC7Z035 0x12
@@ -32,9 +34,11 @@
/* Device Image Sizes */
#define XILINX_XC7Z007S_SIZE 16669920/8
#define XILINX_XC7Z010_SIZE 16669920/8
+#define XILINX_XC7Z010_LR_SIZE 16669920/8
#define XILINX_XC7Z012S_SIZE 28085344/8
#define XILINX_XC7Z014S_SIZE 32364512/8
#define XILINX_XC7Z015_SIZE 28085344/8
+#define XILINX_XC7Z020_LR_SIZE 32364512/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z035_SIZE 106571232/8
@@ -44,9 +48,11 @@
/* Device Names */
#define XILINX_XC7Z007S_NAME "7z007s"
#define XILINX_XC7Z010_NAME "7z010"
+#define XILINX_XC7Z010_LR_NAME "xc7z010_lr"
#define XILINX_XC7Z012S_NAME "7z012s"
#define XILINX_XC7Z014S_NAME "7z014s"
#define XILINX_XC7Z015_NAME "7z015"
+#define XILINX_XC7Z020_LR_NAME "xa7z020_lr"
#define XILINX_XC7Z020_NAME "7z020"
#define XILINX_XC7Z030_NAME "7z030"
#define XILINX_XC7Z035_NAME "7z035"