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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8550 Peripheral Authentication Service
8
9maintainers:
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description:
13 Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware
14 on the Qualcomm DSP Hexagon cores.
15
16properties:
17 compatible:
18 enum:
19 - qcom,sm8550-adsp-pas
20 - qcom,sm8550-cdsp-pas
21 - qcom,sm8550-mpss-pas
Tom Rini6bb92fc2024-05-20 09:54:58 -060022 - qcom,sm8650-adsp-pas
23 - qcom,sm8650-cdsp-pas
24 - qcom,sm8650-mpss-pas
25 - qcom,x1e80100-adsp-pas
26 - qcom,x1e80100-cdsp-pas
Tom Rini53633a82024-02-29 12:33:36 -050027
28 reg:
29 maxItems: 1
30
31 clocks:
32 items:
33 - description: XO clock
34
35 clock-names:
36 items:
37 - const: xo
38
39 qcom,qmp:
40 $ref: /schemas/types.yaml#/definitions/phandle
41 description: Reference to the AOSS side-channel message RAM.
42
43 smd-edge: false
44
45 firmware-name:
46 $ref: /schemas/types.yaml#/definitions/string-array
47 items:
48 - description: Firmware name of the Hexagon core
49 - description: Firmware name of the Hexagon Devicetree
50
51 memory-region:
52 minItems: 2
53 items:
54 - description: Memory region for main Firmware authentication
55 - description: Memory region for Devicetree Firmware authentication
56 - description: DSM Memory region
Tom Rini6bb92fc2024-05-20 09:54:58 -060057 - description: DSM Memory region 2
58 - description: Memory region for Qlink Logging
Tom Rini53633a82024-02-29 12:33:36 -050059
60required:
61 - compatible
62 - reg
63 - memory-region
64
65allOf:
66 - $ref: /schemas/remoteproc/qcom,pas-common.yaml#
67 - if:
68 properties:
69 compatible:
70 enum:
71 - qcom,sm8550-adsp-pas
72 - qcom,sm8550-cdsp-pas
Tom Rini6bb92fc2024-05-20 09:54:58 -060073 - qcom,sm8650-adsp-pas
74 - qcom,x1e80100-adsp-pas
75 - qcom,x1e80100-cdsp-pas
Tom Rini53633a82024-02-29 12:33:36 -050076 then:
77 properties:
78 interrupts:
79 maxItems: 5
80 interrupt-names:
81 maxItems: 5
82 memory-region:
83 maxItems: 2
Tom Rini6bb92fc2024-05-20 09:54:58 -060084 - if:
85 properties:
86 compatible:
87 enum:
88 - qcom,sm8650-cdsp-pas
89 then:
90 properties:
91 interrupts:
92 maxItems: 5
93 interrupt-names:
94 maxItems: 5
95 memory-region:
96 minItems: 3
97 maxItems: 3
98 - if:
99 properties:
100 compatible:
101 enum:
102 - qcom,sm8550-mpss-pas
103 then:
Tom Rini53633a82024-02-29 12:33:36 -0500104 properties:
105 interrupts:
106 minItems: 6
107 interrupt-names:
108 minItems: 6
109 memory-region:
110 minItems: 3
Tom Rini6bb92fc2024-05-20 09:54:58 -0600111 maxItems: 3
112 - if:
113 properties:
114 compatible:
115 enum:
116 - qcom,sm8650-mpss-pas
117 then:
118 properties:
119 interrupts:
120 minItems: 6
121 interrupt-names:
122 minItems: 6
123 memory-region:
124 minItems: 5
125 maxItems: 5
Tom Rini53633a82024-02-29 12:33:36 -0500126
127 - if:
128 properties:
129 compatible:
130 enum:
131 - qcom,sm8550-adsp-pas
Tom Rini6bb92fc2024-05-20 09:54:58 -0600132 - qcom,sm8650-adsp-pas
133 - qcom,x1e80100-adsp-pas
Tom Rini53633a82024-02-29 12:33:36 -0500134 then:
135 properties:
136 power-domains:
137 items:
138 - description: LCX power domain
139 - description: LMX power domain
140 power-domain-names:
141 items:
142 - const: lcx
143 - const: lmx
144
145 - if:
146 properties:
147 compatible:
148 enum:
149 - qcom,sm8550-mpss-pas
Tom Rini6bb92fc2024-05-20 09:54:58 -0600150 - qcom,sm8650-mpss-pas
Tom Rini53633a82024-02-29 12:33:36 -0500151 then:
152 properties:
153 power-domains:
154 items:
155 - description: CX power domain
156 - description: MSS power domain
157 power-domain-names:
158 items:
159 - const: cx
160 - const: mss
161 - if:
162 properties:
163 compatible:
164 enum:
165 - qcom,sm8550-cdsp-pas
Tom Rini6bb92fc2024-05-20 09:54:58 -0600166 - qcom,sm8650-cdsp-pas
167 - qcom,x1e80100-cdsp-pas
Tom Rini53633a82024-02-29 12:33:36 -0500168 then:
169 properties:
170 power-domains:
171 items:
172 - description: CX power domain
173 - description: MXC power domain
174 - description: NSP power domain
175 power-domain-names:
176 items:
177 - const: cx
178 - const: mxc
179 - const: nsp
180
181unevaluatedProperties: false
182
183examples:
184 - |
185 #include <dt-bindings/clock/qcom,rpmh.h>
186 #include <dt-bindings/interrupt-controller/irq.h>
187 #include <dt-bindings/mailbox/qcom-ipcc.h>
188
189 remoteproc@30000000 {
190 compatible = "qcom,sm8550-adsp-pas";
191 reg = <0x030000000 0x100>;
192
193 clocks = <&rpmhcc RPMH_CXO_CLK>;
194 clock-names = "xo";
195
196 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
197 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
198 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
199 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
200 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
201 interrupt-names = "wdog", "fatal", "ready",
202 "handover", "stop-ack";
203
204 memory-region = <&adsp_mem>, <&dtb_adsp_mem>;
205
206 firmware-name = "qcom/sm8550/adsp.mbn",
207 "qcom/sm8550/adsp_dtb.mbn";
208
209 power-domains = <&rpmhpd_sm8550_lcx>,
210 <&rpmhpd_sm8550_lmx>;
211 power-domain-names = "lcx", "lmx";
212
213 qcom,qmp = <&aoss_qmp>;
214 qcom,smem-states = <&smp2p_adsp_out 0>;
215 qcom,smem-state-names = "stop";
216
217 glink-edge {
218 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
219 IPCC_MPROC_SIGNAL_GLINK_QMP
220 IRQ_TYPE_EDGE_RISING>;
221 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>;
222
223 label = "lpass";
224 qcom,remote-pid = <2>;
225
226 /* ... */
227 };
228 };