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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / dts / upstream / Bindings / phy / realtek,usb2phy.yaml
blob: 9911ada39ee7a1b2c5780e6bb66595d3cf861e81 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2023 Realtek Semiconductor Corporation
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/realtek,usb2phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Realtek DHC SoCs USB 2.0 PHY
9
10maintainers:
11 - Stanley Chang <stanley_chang@realtek.com>
12
13description: |
14 Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoCs.
15 The USB 2.0 PHY driver is designed to support the XHCI controller. The SoCs
16 support multiple XHCI controllers. One PHY device node maps to one XHCI
17 controller.
18
19 RTD1295/RTD1619 SoCs USB
20 The USB architecture includes three XHCI controllers.
21 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on some
22 controllers.
23 XHCI controller#0 -- usb2phy -- phy#0
24 |- usb3phy -- phy#0
25 XHCI controller#1 -- usb2phy -- phy#0
26 XHCI controller#2 -- usb2phy -- phy#0
27 |- usb3phy -- phy#0
28
29 RTD1395 SoCs USB
30 The USB architecture includes two XHCI controllers.
31 The controller#0 has one USB 2.0 PHY. The controller#1 includes two USB 2.0
32 PHY.
33 XHCI controller#0 -- usb2phy -- phy#0
34 XHCI controller#1 -- usb2phy -- phy#0
35 |- phy#1
36
37 RTD1319/RTD1619b SoCs USB
38 The USB architecture includes three XHCI controllers.
39 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
40 XHCI controller#0 -- usb2phy -- phy#0
41 XHCI controller#1 -- usb2phy -- phy#0
42 XHCI controller#2 -- usb2phy -- phy#0
43 |- usb3phy -- phy#0
44
45 RTD1319d SoCs USB
46 The USB architecture includes three XHCI controllers.
47 Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
48 XHCI controller#0 -- usb2phy -- phy#0
49 |- usb3phy -- phy#0
50 XHCI controller#1 -- usb2phy -- phy#0
51 XHCI controller#2 -- usb2phy -- phy#0
52
53 RTD1312c/RTD1315e SoCs USB
54 The USB architecture includes three XHCI controllers.
55 Each XHCI maps to one USB 2.0 PHY.
56 XHCI controller#0 -- usb2phy -- phy#0
57 XHCI controller#1 -- usb2phy -- phy#0
58 XHCI controller#2 -- usb2phy -- phy#0
59
60properties:
61 compatible:
62 enum:
63 - realtek,rtd1295-usb2phy
64 - realtek,rtd1312c-usb2phy
65 - realtek,rtd1315e-usb2phy
66 - realtek,rtd1319-usb2phy
67 - realtek,rtd1319d-usb2phy
68 - realtek,rtd1395-usb2phy
69 - realtek,rtd1395-usb2phy-2port
70 - realtek,rtd1619-usb2phy
71 - realtek,rtd1619b-usb2phy
72
73 reg:
74 items:
75 - description: PHY data registers
76 - description: PHY control registers
77
78 "#phy-cells":
79 const: 0
80
81 nvmem-cells:
82 maxItems: 2
83 description:
84 Phandles to nvmem cell that contains the trimming data.
85 If unspecified, default value is used.
86
87 nvmem-cell-names:
88 items:
89 - const: usb-dc-cal
90 - const: usb-dc-dis
91 description:
92 The following names, which correspond to each nvmem-cells.
93 usb-dc-cal is the driving level for each phy specified via efuse.
94 usb-dc-dis is the disconnection level for each phy specified via efuse.
95
96 realtek,inverse-hstx-sync-clock:
97 description:
98 For one of the phys of RTD1619b SoC, the synchronous clock of the
99 high-speed tx must be inverted.
100 type: boolean
101
102 realtek,driving-level:
103 description:
104 Control the magnitude of High speed Dp/Dm output swing (mV).
105 For a different board or port, the original magnitude maybe not meet
106 the specification. In this situation we can adjust the value to meet
107 the specification.
108 $ref: /schemas/types.yaml#/definitions/uint32
109 default: 8
110 minimum: 0
111 maximum: 31
112
113 realtek,driving-level-compensate:
114 description:
115 For RTD1315e SoC, the driving level can be adjusted by reading the
116 efuse table. This property provides drive compensation.
117 If the magnitude of High speed Dp/Dm output swing still not meet the
118 specification, then we can set this value to meet the specification.
119 $ref: /schemas/types.yaml#/definitions/int32
120 default: 0
121 minimum: -8
122 maximum: 8
123
124 realtek,disconnection-compensate:
125 description:
126 This adjusts the disconnection level compensation for the different
127 boards with different disconnection level.
128 $ref: /schemas/types.yaml#/definitions/int32
129 default: 0
130 minimum: -8
131 maximum: 8
132
133required:
134 - compatible
135 - reg
136 - "#phy-cells"
137
138allOf:
139 - if:
140 not:
141 properties:
142 compatible:
143 contains:
144 enum:
145 - realtek,rtd1619b-usb2phy
146 then:
147 properties:
148 realtek,inverse-hstx-sync-clock: false
149
150 - if:
151 not:
152 properties:
153 compatible:
154 contains:
155 enum:
156 - realtek,rtd1315e-usb2phy
157 then:
158 properties:
159 realtek,driving-level-compensate: false
160
161additionalProperties: false
162
163examples:
164 - |
165 usb-phy@13214 {
166 compatible = "realtek,rtd1619b-usb2phy";
167 reg = <0x13214 0x4>, <0x28280 0x4>;
168 #phy-cells = <0>;
169 nvmem-cells = <&otp_usb_port0_dc_cal>, <&otp_usb_port0_dc_dis>;
170 nvmem-cell-names = "usb-dc-cal", "usb-dc-dis";
171
172 realtek,inverse-hstx-sync-clock;
173 realtek,driving-level = <0xa>;
174 realtek,disconnection-compensate = <(-1)>;
175 };