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git01.mediatek.com / filogic / uboot / df41fc634d9e2e7899dc1023a7390708e6d8b886 / . / arch / arm / mach-tegra / cmd_enterrcm.c
blob: 8fa1207e97a8adf17f7cea161895b19fa8d22542 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]2/*
Thierry Redingce7eb162019-04-15 11:32:25 +0200[diff] [blame]3 * Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]4 *
5 * Derived from code (arch/arm/lib/reset.c) that is:
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <mgroeger@sysgo.de>
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Alex Zuepke <azu@sysgo.de>
14 *
15 * (C) Copyright 2002
16 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
17 *
18 * (C) Copyright 2004
19 * DAVE Srl
20 * http://www.dave-tech.it
21 * http://www.wawnet.biz
22 * mailto:info@wawnet.biz
23 *
24 * (C) Copyright 2004 Texas Insturments
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]25 */
26
Simon Glassed38aef2020-05-10 11:40:03 -0600[diff] [blame]27#include <command.h>
Simon Glassafb02152019-12-28 10:45:01 -0700[diff] [blame]28#include <cpu_func.h>
Simon Glass8f3f7612019-11-14 12:57:42 -0700[diff] [blame]29#include <irq_func.h>
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]30#include <asm/arch/tegra.h>
31#include <asm/arch-tegra/pmc.h>
Simon Glassdbd79542020-05-10 11:40:11 -0600[diff] [blame]32#include <linux/delay.h>
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]33
Simon Glassed38aef2020-05-10 11:40:03 -0600[diff] [blame]34static int do_enterrcm(struct cmd_tbl *cmdtp, int flag, int argc,
35 char *const argv[])
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]36{
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]37 puts("Entering RCM...\n");
38 udelay(50000);
39
Thierry Redingce7eb162019-04-15 11:32:25 +0200[diff] [blame]40 tegra_pmc_writel(2, PMC_SCRATCH0);
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]41 disable_interrupts();
Harald Seiler6f14d5f2020-12-15 16:47:52 +0100[diff] [blame]42 reset_cpu();
Stephen Warren3c7643c2012-06-04 09:23:55 +0000[diff] [blame]43
44 return 0;
45}
46
47U_BOOT_CMD(
48 enterrcm, 1, 0, do_enterrcm,
49 "reset Tegra and enter USB Recovery Mode",
50 ""
51);