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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +02002/*
3 * LPC32xx MLC NAND flash controller driver
4 *
5 * (C) Copyright 2014 3ADEV <http://3adev.com>
6 * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
7 *
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +02008 * NOTE:
9 *
10 * The MLC NAND flash controller provides hardware Reed-Solomon ECC
11 * covering in- and out-of-band data together. Therefore, in- and out-
12 * of-band data must be written together in order to have a valid ECC.
13 *
14 * Consequently, pages with meaningful in-band data are written with
15 * blank (all-ones) out-of-band data and a valid ECC, and any later
16 * out-of-band data write will void the ECC.
17 *
18 * Therefore, code which reads such late-written out-of-band data
19 * should not rely on the ECC validity.
20 */
21
22#include <common.h>
23#include <nand.h>
Simon Glassdbd79542020-05-10 11:40:11 -060024#include <linux/delay.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090025#include <linux/errno.h>
Tom Rini3bde7e22021-09-22 14:50:35 -040026#include <linux/mtd/rawnand.h>
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +020027#include <asm/io.h>
28#include <nand.h>
29#include <asm/arch/clk.h>
30#include <asm/arch/sys_proto.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060031#include <linux/printk.h>
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +020032
33/*
34 * MLC NAND controller registers.
35 */
36struct lpc32xx_nand_mlc_registers {
37 u8 buff[32768]; /* controller's serial data buffer */
38 u8 data[32768]; /* NAND's raw data buffer */
39 u32 cmd;
40 u32 addr;
41 u32 ecc_enc_reg;
42 u32 ecc_dec_reg;
43 u32 ecc_auto_enc_reg;
44 u32 ecc_auto_dec_reg;
45 u32 rpr;
46 u32 wpr;
47 u32 rubp;
48 u32 robp;
49 u32 sw_wp_add_low;
50 u32 sw_wp_add_hig;
51 u32 icr;
52 u32 time_reg;
53 u32 irq_mr;
54 u32 irq_sr;
55 u32 lock_pr;
56 u32 isr;
57 u32 ceh;
58};
59
60/* LOCK_PR register defines */
61#define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */
62
63/* ICR defines */
64#define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */
65#define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
66
67/* CEH defines */
68#define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */
69
70/* ISR register defines */
71#define ISR_NAND_READY 0x00000001
72#define ISR_CONTROLLER_READY 0x00000002
73#define ISR_ECC_READY 0x00000004
74#define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
75#define ISR_DECODER_FAILURE 0x00000040
76#define ISR_DECODER_ERROR 0x00000008
77
78/* time-out for NAND chip / controller loops, in us */
79#define LPC32X_NAND_TIMEOUT 5000
80
81/*
82 * There is a single instance of the NAND MLC controller
83 */
84
85static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
86 = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
87
Tom Rini6a5dccc2022-11-16 13:10:41 -050088#if !defined(CFG_SYS_MAX_NAND_CHIPS)
89#define CFG_SYS_MAX_NAND_CHIPS 1
Vladimir Zapolskiy56702372018-10-19 03:21:05 +030090#endif
91
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +020092#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
93
94/**
95 * OOB data in each small page are 6 'free' then 10 ECC bytes.
96 * To make things easier, when reading large pages, the four pages'
97 * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
98 * while the the four ECC bytes are groupe in its last 40 bytes.
99 *
100 * The struct below represents how free vs ecc oob bytes are stored
101 * in the buffer.
102 *
103 * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
104 */
105
106struct lpc32xx_oob {
107 struct {
108 uint8_t free_oob_bytes[6];
109 } free[4];
110 struct {
111 uint8_t ecc_oob_bytes[10];
112 } ecc[4];
113};
114
115/*
116 * Initialize the controller
117 */
118
119static void lpc32xx_nand_init(void)
120{
121 unsigned int clk;
122
123 /* Configure controller for no software write protection, x8 bus
124 width, large block device, and 4 address words */
125
126 /* unlock controller registers with magic key */
127 writel(LOCK_PR_UNLOCK_KEY,
128 &lpc32xx_nand_mlc_registers->lock_pr);
129
130 /* enable large blocks and large NANDs */
131 writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
132 &lpc32xx_nand_mlc_registers->icr);
133
134 /* Make sure MLC interrupts are disabled */
135 writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
136
137 /* Normal chip enable operation */
138 writel(CEH_NORMAL_CE,
139 &lpc32xx_nand_mlc_registers->ceh);
140
141 /* Setup NAND timing */
142 clk = get_hclk_clk_rate();
143
144 writel(
Tom Rini59cbfca2022-12-04 10:04:38 -0500145 clkdiv(CFG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
Tom Rini326ca482022-12-04 10:04:34 -0500146 clkdiv(CFG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
Tom Riniac8d5712022-12-04 10:04:35 -0500147 clkdiv(CFG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
Tom Rini2f54d772022-12-04 10:04:36 -0500148 clkdiv(CFG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
Tom Rini045a2952022-12-04 10:04:37 -0500149 clkdiv(CFG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
Tom Rinid67a37f2022-12-04 10:04:39 -0500150 clkdiv(CFG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
Tom Rini86785602022-12-04 10:04:40 -0500151 clkdiv(CFG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200152 &lpc32xx_nand_mlc_registers->time_reg);
153}
154
155#if !defined(CONFIG_SPL_BUILD)
156
157/**
158 * lpc32xx_cmd_ctrl - write command to either cmd or data register
159 */
160
161static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
162 unsigned int ctrl)
163{
164 if (cmd == NAND_CMD_NONE)
165 return;
166
167 if (ctrl & NAND_CLE)
168 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
169 else if (ctrl & NAND_ALE)
170 writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
171}
172
173/**
174 * lpc32xx_read_byte - read a byte from the NAND
175 * @mtd: MTD device structure
176 */
177
178static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
179{
180 return readb(&lpc32xx_nand_mlc_registers->data);
181}
182
183/**
184 * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
185 * @mtd: MTD device structure
186 * @mode: mode to set the ECC HW to.
187 */
188
189static int lpc32xx_dev_ready(struct mtd_info *mtd)
190{
191 /* means *controller* ready for us */
192 int status = readl(&lpc32xx_nand_mlc_registers->isr);
193 return status & ISR_CONTROLLER_READY;
194}
195
196/**
197 * ECC layout -- this is needed whatever ECC mode we are using.
198 * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
199 * To make U-Boot's life easier, we pack 'useable' OOB at the
200 * front and R/S ECC at the back.
201 */
202
203static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
204 .eccbytes = 40,
205 .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
206 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
207 44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
208 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
209 },
210 .oobfree = {
211 /* bytes 0 and 1 are used for the bad block marker */
212 {
213 .offset = 2,
214 .length = 22
215 },
216 }
217};
218
219/**
220 * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
221 * @mtd: mtd info structure
222 * @chip: nand chip info structure
223 * @buf: buffer to store read data
224 * @oob_required: caller requires OOB data read to chip->oob_poi
225 * @page: page number to read
226 *
227 * Use large block Auto Decode Read Mode(1) as described in User Manual
228 * section 8.6.2.1.
229 *
230 * The initial Read Mode and Read Start commands are sent by the caller.
231 *
232 * ECC will be false if out-of-band data has been updated since in-band
233 * data was initially written.
234 */
235
236static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
237 struct nand_chip *chip, uint8_t *buf, int oob_required,
238 int page)
239{
240 unsigned int i, status, timeout, err, max_bitflips = 0;
241 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
242
243 /* go through all four small pages */
244 for (i = 0; i < 4; i++) {
245 /* start auto decode (reads 528 NAND bytes) */
246 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
247 /* wait for controller to return to ready state */
248 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
249 status = readl(&lpc32xx_nand_mlc_registers->isr);
250 if (status & ISR_CONTROLLER_READY)
251 break;
252 udelay(1);
253 }
254 /* if decoder failed, return failure */
255 if (status & ISR_DECODER_FAILURE)
256 return -1;
257 /* keep count of maximum bitflips performed */
258 if (status & ISR_DECODER_ERROR) {
259 err = ISR_DECODER_ERRORS(status);
260 if (err > max_bitflips)
261 max_bitflips = err;
262 }
263 /* copy first 512 bytes into buffer */
264 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
265 /* copy next 6 bytes at front of OOB buffer */
266 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
267 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
268 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
269 }
270 return max_bitflips;
271}
272
273/**
274 * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
275 * @mtd: mtd info structure
276 * @chip: nand chip info structure
277 * @buf: buffer to store read data
278 * @oob_required: caller requires OOB data read to chip->oob_poi
279 * @page: page number to read
280 *
281 * Read NAND directly; can read pages with invalid ECC.
282 */
283
284static int lpc32xx_read_page_raw(struct mtd_info *mtd,
285 struct nand_chip *chip, uint8_t *buf, int oob_required,
286 int page)
287{
288 unsigned int i, status, timeout;
289 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
290
291 /* when we get here we've already had the Read Mode(1) */
292
293 /* go through all four small pages */
294 for (i = 0; i < 4; i++) {
295 /* wait for NAND to return to ready state */
296 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
297 status = readl(&lpc32xx_nand_mlc_registers->isr);
298 if (status & ISR_NAND_READY)
299 break;
300 udelay(1);
301 }
302 /* if NAND stalled, return failure */
303 if (!(status & ISR_NAND_READY))
304 return -1;
305 /* copy first 512 bytes into buffer */
306 memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
307 /* copy next 6 bytes at front of OOB buffer */
308 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
309 /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
310 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
311 }
312 return 0;
313}
314
315/**
316 * lpc32xx_read_oob - read out-of-band data
317 * @mtd: mtd info structure
318 * @chip: nand chip info structure
319 * @page: page number to read
320 *
321 * Read out-of-band data. User Manual section 8.6.4 suggests using Read
322 * Mode(3) which the controller will turn into a Read Mode(1) internally
323 * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
324 * directly.
325 *
326 * ECC covers in- and out-of-band data and was written when out-of-band
327 * data was blank. Therefore, if the out-of-band being read here is not
328 * blank, then the ECC will be false and the read will return bitflips,
329 * even in case of ECC failure where we will return 5 bitflips. The
330 * caller should be prepared to handle this.
331 */
332
333static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
334 int page)
335{
336 unsigned int i, status, timeout, err, max_bitflips = 0;
337 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
338
339 /* No command was sent before calling read_oob() so send one */
340
341 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
342
343 /* go through all four small pages */
344 for (i = 0; i < 4; i++) {
345 /* start auto decode (reads 528 NAND bytes) */
346 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
347 /* wait for controller to return to ready state */
348 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
349 status = readl(&lpc32xx_nand_mlc_registers->isr);
350 if (status & ISR_CONTROLLER_READY)
351 break;
352 udelay(1);
353 }
354 /* if decoder failure, count 'one too many' bitflips */
355 if (status & ISR_DECODER_FAILURE)
356 max_bitflips = 5;
357 /* keep count of maximum bitflips performed */
358 if (status & ISR_DECODER_ERROR) {
359 err = ISR_DECODER_ERRORS(status);
360 if (err > max_bitflips)
361 max_bitflips = err;
362 }
363 /* set read pointer to OOB area */
364 writel(0, &lpc32xx_nand_mlc_registers->robp);
365 /* copy next 6 bytes at front of OOB buffer */
366 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
367 /* copy next 10 bytes (R/S ECC) at back of OOB buffer */
368 memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
369 }
370 return max_bitflips;
371}
372
373/**
374 * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
375 * @mtd: mtd info structure
376 * @chip: nand chip info structure
377 * @buf: data buffer
378 * @oob_required: must write chip->oob_poi to OOB
379 *
380 * Use large block Auto Encode as per User Manual section 8.6.4.
381 *
382 * The initial Write Serial Input and final Auto Program commands are
383 * sent by the caller.
384 */
385
386static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
Scott Wood46e13102016-05-30 13:57:57 -0500387 struct nand_chip *chip, const uint8_t *buf, int oob_required,
388 int page)
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200389{
390 unsigned int i, status, timeout;
391 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
392
393 /* when we get here we've already had the SEQIN */
394 for (i = 0; i < 4; i++) {
395 /* start encode (expects 518 writes to buff) */
396 writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
397 /* copy first 512 bytes from buffer */
398 memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
399 /* copy next 6 bytes from OOB buffer -- excluding ECC */
400 memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
401 /* wait for ECC to return to ready state */
402 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
403 status = readl(&lpc32xx_nand_mlc_registers->isr);
404 if (status & ISR_ECC_READY)
405 break;
406 udelay(1);
407 }
408 /* if ECC stalled, return failure */
409 if (!(status & ISR_ECC_READY))
410 return -1;
411 /* Trigger auto encode (writes 528 bytes to NAND) */
412 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
413 /* wait for controller to return to ready state */
414 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
415 status = readl(&lpc32xx_nand_mlc_registers->isr);
416 if (status & ISR_CONTROLLER_READY)
417 break;
418 udelay(1);
419 }
420 /* if controller stalled, return error */
421 if (!(status & ISR_CONTROLLER_READY))
422 return -1;
423 }
424 return 0;
425}
426
427/**
428 * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
429 * @mtd: mtd info structure
430 * @chip: nand chip info structure
431 * @buf: buffer to store read data
432 * @oob_required: caller requires OOB data read to chip->oob_poi
433 * @page: page number to read
434 *
435 * Use large block write but without encode.
436 *
437 * The initial Write Serial Input and final Auto Program commands are
438 * sent by the caller.
439 *
440 * This function will write the full out-of-band data, including the
441 * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
442 */
443
444static int lpc32xx_write_page_raw(struct mtd_info *mtd,
Scott Wood46e13102016-05-30 13:57:57 -0500445 struct nand_chip *chip, const uint8_t *buf, int oob_required,
446 int page)
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200447{
448 unsigned int i;
449 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
450
451 /* when we get here we've already had the Read Mode(1) */
452 for (i = 0; i < 4; i++) {
453 /* copy first 512 bytes from buffer */
454 memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
455 /* copy next 6 bytes into OOB buffer -- excluding ECC */
456 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
457 /* copy next 10 bytes into OOB buffer -- that is 'ECC' */
458 memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
459 }
460 return 0;
461}
462
463/**
464 * lpc32xx_write_oob - write out-of-band data
465 * @mtd: mtd info structure
466 * @chip: nand chip info structure
467 * @page: page number to read
468 *
469 * Since ECC covers in- and out-of-band data, writing out-of-band data
470 * with ECC will render the page ECC wrong -- or, if the page was blank,
471 * then it will produce a good ECC but a later in-band data write will
472 * render it wrong.
473 *
474 * Therefore, do not compute or write any ECC, and always return success.
475 *
476 * This implies that we do four writes, since non-ECC out-of-band data
477 * are not contiguous in a large page.
478 */
479
480static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
481 int page)
482{
483 /* update oob on all 4 subpages in sequence */
484 unsigned int i, status, timeout;
485 struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
486
487 for (i = 0; i < 4; i++) {
488 /* start data input */
489 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
490 /* copy 6 non-ECC out-of-band bytes directly into NAND */
491 memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
492 /* program page */
493 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
494 /* wait for NAND to return to ready state */
495 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
496 status = readl(&lpc32xx_nand_mlc_registers->isr);
497 if (status & ISR_NAND_READY)
498 break;
499 udelay(1);
500 }
501 /* if NAND stalled, return error */
502 if (!(status & ISR_NAND_READY))
503 return -1;
504 }
505 return 0;
506}
507
508/**
509 * lpc32xx_waitfunc - wait until a command is done
510 * @mtd: MTD device structure
511 * @chip: NAND chip structure
512 *
513 * Wait for controller and FLASH to both be ready.
514 */
515
516static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
517{
518 int status;
519 unsigned int timeout;
520 /* wait until both controller and NAND are ready */
521 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
522 status = readl(&lpc32xx_nand_mlc_registers->isr);
523 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
524 == (ISR_CONTROLLER_READY || ISR_NAND_READY))
525 break;
526 udelay(1);
527 }
528 /* if controller or NAND stalled, return error */
529 if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
530 != (ISR_CONTROLLER_READY || ISR_NAND_READY))
531 return -1;
532 /* write NAND status command */
533 writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
534 /* read back status and return it */
535 return readb(&lpc32xx_nand_mlc_registers->data);
536}
537
538/*
539 * We are self-initializing, so we need our own chip struct
540 */
541
542static struct nand_chip lpc32xx_chip;
543
544/*
545 * Initialize the controller
546 */
547
548void board_nand_init(void)
549{
Boris Brezillon3b5f8842016-06-15 20:56:10 +0200550 struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200551 int ret;
552
553 /* Set all BOARDSPECIFIC (actually core-specific) fields */
554
555 lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
556 lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
557 lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
558 /* do not set init_size: nand_base.c will read sizes from chip */
559 lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
560 /* do not set setup_read_retry: this is NAND-chip-specific */
561 /* do not set chip_delay: we have dev_ready defined. */
562 lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
563
564 /* Set needed ECC fields */
565
566 lpc32xx_chip.ecc.mode = NAND_ECC_HW;
567 lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
568 lpc32xx_chip.ecc.size = 512;
569 lpc32xx_chip.ecc.bytes = 10;
570 lpc32xx_chip.ecc.strength = 4;
571 lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
572 lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
573 lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
574 lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
575 lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
576 lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
577 lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
578
579 lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
580
581 /* BBT options: read from last two pages */
582 lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
583 | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
584 | NAND_BBT_WRITE;
585
586 /* Initialize NAND interface */
587 lpc32xx_nand_init();
588
589 /* identify chip */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500590 ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200591 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900592 pr_err("nand_scan_ident returned %i", ret);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200593 return;
594 }
595
596 /* finish scanning the chip */
597 ret = nand_scan_tail(mtd);
598 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900599 pr_err("nand_scan_tail returned %i", ret);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200600 return;
601 }
602
603 /* chip is good, register it */
Scott Wood2c1b7e12016-05-30 13:57:55 -0500604 ret = nand_register(0, mtd);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200605 if (ret)
Masahiro Yamada81e10422017-09-16 14:10:41 +0900606 pr_err("nand_register returned %i", ret);
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +0200607}
608
609#else /* defined(CONFIG_SPL_BUILD) */
610
611void nand_init(void)
612{
613 /* enable NAND controller */
614 lpc32xx_mlc_nand_init();
615 /* initialize NAND controller */
616 lpc32xx_nand_init();
617}
618
619void nand_deselect(void)
620{
621 /* nothing to do, but SPL requires this function */
622}
623
624static int read_single_page(uint8_t *dest, int page,
625 struct lpc32xx_oob *oob)
626{
627 int status, i, timeout, err, max_bitflips = 0;
628
629 /* enter read mode */
630 writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
631 /* send column (lsb then MSB) and page (lsb to MSB) */
632 writel(0, &lpc32xx_nand_mlc_registers->addr);
633 writel(0, &lpc32xx_nand_mlc_registers->addr);
634 writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
635 writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
636 writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
637 /* start reading */
638 writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
639
640 /* large page auto decode read */
641 for (i = 0; i < 4; i++) {
642 /* start auto decode (reads 528 NAND bytes) */
643 writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
644 /* wait for controller to return to ready state */
645 for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
646 status = readl(&lpc32xx_nand_mlc_registers->isr);
647 if (status & ISR_CONTROLLER_READY)
648 break;
649 udelay(1);
650 }
651 /* if controller stalled, return error */
652 if (!(status & ISR_CONTROLLER_READY))
653 return -1;
654 /* if decoder failure, return error */
655 if (status & ISR_DECODER_FAILURE)
656 return -1;
657 /* keep count of maximum bitflips performed */
658 if (status & ISR_DECODER_ERROR) {
659 err = ISR_DECODER_ERRORS(status);
660 if (err > max_bitflips)
661 max_bitflips = err;
662 }
663 /* copy first 512 bytes into buffer */
664 memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
665 /* copy next 6 bytes bytes into OOB buffer */
666 memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
667 }
668 return max_bitflips;
669}
670
671/*
672 * Load U-Boot signed image.
673 * This loads an image from NAND, skipping bad blocks.
674 * A block is declared bad if at least one of its readable pages has
675 * a bad block marker in its OOB at position 0.
676 * If all pages ion a block are unreadable, the block is considered
677 * bad (i.e., assumed not to be part of the image) and skipped.
678 *
679 * IMPORTANT NOTE:
680 *
681 * If the first block of the image is fully unreadable, it will be
682 * ignored and skipped as if it had been marked bad. If it was not
683 * actually marked bad at the time of writing the image, the resulting
684 * image loaded will lack a header and magic number. It could thus be
685 * considered as a raw, headerless, image and SPL might erroneously
686 * jump into it.
687 *
688 * In order to avoid this risk, LPC32XX-based boards which use this
689 * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
690 */
691
692#define BYTES_PER_PAGE 2048
693#define PAGES_PER_BLOCK 64
694#define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
695#define PAGES_PER_CHIP_MAX 524288
696
697int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
698{
699 int bytes_left = size;
700 int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
701 int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
702 int block = 0;
703 int page = offs / BYTES_PER_PAGE;
704 /* perform reads block by block */
705 while (blocks_left) {
706 /* compute first page number to read */
707 void *block_page_dst = dst;
708 /* read at most one block, possibly less */
709 int block_bytes_left = bytes_left;
710 if (block_bytes_left > BYTES_PER_BLOCK)
711 block_bytes_left = BYTES_PER_BLOCK;
712 /* keep track of good, failed, and "bad" pages */
713 int block_pages_good = 0;
714 int block_pages_bad = 0;
715 int block_pages_err = 0;
716 /* we shall read a full block of pages, maybe less */
717 int block_pages_left = pages_left;
718 if (block_pages_left > PAGES_PER_BLOCK)
719 block_pages_left = PAGES_PER_BLOCK;
720 int block_pages = block_pages_left;
721 int block_page = page;
722 /* while pages are left and the block is not known as bad */
723 while ((block_pages > 0) && (block_pages_bad == 0)) {
724 /* we will read OOB, too, for bad block markers */
725 struct lpc32xx_oob oob;
726 /* read page */
727 int res = read_single_page(block_page_dst, block_page,
728 &oob);
729 /* count readable pages */
730 if (res >= 0) {
731 /* this page is good */
732 block_pages_good++;
733 /* this page is bad */
734 if ((oob.free[0].free_oob_bytes[0] != 0xff)
735 | (oob.free[0].free_oob_bytes[1] != 0xff))
736 block_pages_bad++;
737 } else
738 /* count errors */
739 block_pages_err++;
740 /* we're done with this page */
741 block_page++;
742 block_page_dst += BYTES_PER_PAGE;
743 if (block_pages)
744 block_pages--;
745 }
746 /* a fully unreadable block is considered bad */
747 if (block_pages_good == 0)
748 block_pages_bad = block_pages_err;
749 /* errors are fatal only in good blocks */
750 if ((block_pages_err > 0) && (block_pages_bad == 0))
751 return -1;
752 /* we keep reads only of good blocks */
753 if (block_pages_bad == 0) {
754 dst += block_bytes_left;
755 bytes_left -= block_bytes_left;
756 pages_left -= block_pages_left;
757 blocks_left--;
758 }
759 /* good or bad, we're done with this block */
760 block++;
761 page += PAGES_PER_BLOCK;
762 }
763
764 /* report success */
765 return 0;
766}
767
768#endif /* CONFIG_SPL_BUILD */