wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * ARM Ltd. |
| 7 | * Philippe Robin, <philippe.robin@arm.com> |
| 8 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 9 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 12 | /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 13 | |
| 14 | #include <common.h> |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 15 | #include <dm.h> |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 16 | #include <errno.h> |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 17 | #include <watchdog.h> |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 18 | #include <asm/io.h> |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 19 | #include <serial.h> |
Masahiro Yamada | 22c97de | 2014-10-24 12:41:19 +0900 | [diff] [blame] | 20 | #include <dm/platform_data/serial_pl01x.h> |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 21 | #include <linux/compiler.h> |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 22 | #include "serial_pl01x_internal.h" |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 23 | #include <fdtdec.h> |
| 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 26 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 27 | #ifndef CONFIG_DM_SERIAL |
| 28 | |
wdenk | da04a8b | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 29 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 30 | static enum pl01x_type pl01x_type __attribute__ ((section(".data"))); |
| 31 | static struct pl01x_regs *base_regs __attribute__ ((section(".data"))); |
wdenk | da04a8b | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 32 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 33 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 34 | #endif |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 35 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 36 | static int pl01x_putc(struct pl01x_regs *regs, char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 37 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 38 | /* Wait until there is space in the FIFO */ |
| 39 | if (readl(®s->fr) & UART_PL01x_FR_TXFF) |
| 40 | return -EAGAIN; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 41 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 42 | /* Send the character */ |
| 43 | writel(c, ®s->dr); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 44 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 45 | return 0; |
| 46 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 47 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 48 | static int pl01x_getc(struct pl01x_regs *regs) |
| 49 | { |
| 50 | unsigned int data; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 51 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 52 | /* Wait until there is data in the FIFO */ |
| 53 | if (readl(®s->fr) & UART_PL01x_FR_RXFE) |
| 54 | return -EAGAIN; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 55 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 56 | data = readl(®s->dr); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 57 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 58 | /* Check for an error flag */ |
| 59 | if (data & 0xFFFFFF00) { |
| 60 | /* Clear the error */ |
| 61 | writel(0xFFFFFFFF, ®s->ecr); |
| 62 | return -1; |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 65 | return (int) data; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 66 | } |
| 67 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 68 | static int pl01x_tstc(struct pl01x_regs *regs) |
| 69 | { |
| 70 | WATCHDOG_RESET(); |
| 71 | return !(readl(®s->fr) & UART_PL01x_FR_RXFE); |
| 72 | } |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 73 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 74 | static int pl01x_generic_serial_init(struct pl01x_regs *regs, |
| 75 | enum pl01x_type type) |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 76 | { |
Vikas Manocha | be14f15 | 2014-11-21 10:34:23 -0800 | [diff] [blame] | 77 | switch (type) { |
| 78 | case TYPE_PL010: |
| 79 | /* disable everything */ |
| 80 | writel(0, ®s->pl010_cr); |
| 81 | break; |
| 82 | case TYPE_PL011: |
Vikas Manocha | ee038e2 | 2014-11-21 10:34:22 -0800 | [diff] [blame] | 83 | /* disable everything */ |
| 84 | writel(0, ®s->pl011_cr); |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 85 | break; |
| 86 | default: |
| 87 | return -EINVAL; |
| 88 | } |
| 89 | |
| 90 | return 0; |
| 91 | } |
| 92 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 93 | static int pl011_set_line_control(struct pl01x_regs *regs) |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 94 | { |
| 95 | unsigned int lcr; |
| 96 | /* |
| 97 | * Internal update of baud rate register require line |
| 98 | * control register write |
| 99 | */ |
| 100 | lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; |
Vikas Manocha | fe96bbd | 2014-11-21 10:34:21 -0800 | [diff] [blame] | 101 | writel(lcr, ®s->pl011_lcrh); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 102 | return 0; |
| 103 | } |
| 104 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 105 | static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type, |
| 106 | int clock, int baudrate) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 107 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 108 | switch (type) { |
| 109 | case TYPE_PL010: { |
| 110 | unsigned int divisor; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 111 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 112 | /* disable everything */ |
| 113 | writel(0, ®s->pl010_cr); |
| 114 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 115 | switch (baudrate) { |
| 116 | case 9600: |
| 117 | divisor = UART_PL010_BAUD_9600; |
| 118 | break; |
| 119 | case 19200: |
| 120 | divisor = UART_PL010_BAUD_9600; |
| 121 | break; |
| 122 | case 38400: |
| 123 | divisor = UART_PL010_BAUD_38400; |
| 124 | break; |
| 125 | case 57600: |
| 126 | divisor = UART_PL010_BAUD_57600; |
| 127 | break; |
| 128 | case 115200: |
| 129 | divisor = UART_PL010_BAUD_115200; |
| 130 | break; |
| 131 | default: |
| 132 | divisor = UART_PL010_BAUD_38400; |
| 133 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 134 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 135 | writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm); |
| 136 | writel(divisor & 0xff, ®s->pl010_lcrl); |
| 137 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 138 | /* |
| 139 | * Set line control for the PL010 to be 8 bits, 1 stop bit, |
| 140 | * no parity, fifo enabled |
| 141 | */ |
| 142 | writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, |
| 143 | ®s->pl010_lcrh); |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 144 | /* Finally, enable the UART */ |
| 145 | writel(UART_PL010_CR_UARTEN, ®s->pl010_cr); |
| 146 | break; |
| 147 | } |
| 148 | case TYPE_PL011: { |
| 149 | unsigned int temp; |
| 150 | unsigned int divider; |
| 151 | unsigned int remainder; |
| 152 | unsigned int fraction; |
| 153 | |
| 154 | /* |
| 155 | * Set baud rate |
| 156 | * |
| 157 | * IBRD = UART_CLK / (16 * BAUD_RATE) |
| 158 | * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) |
| 159 | * / (16 * BAUD_RATE)) |
| 160 | */ |
| 161 | temp = 16 * baudrate; |
| 162 | divider = clock / temp; |
| 163 | remainder = clock % temp; |
| 164 | temp = (8 * remainder) / baudrate; |
| 165 | fraction = (temp >> 1) + (temp & 1); |
| 166 | |
| 167 | writel(divider, ®s->pl011_ibrd); |
| 168 | writel(fraction, ®s->pl011_fbrd); |
| 169 | |
Linus Walleij | 70864f6 | 2015-04-21 15:10:06 +0200 | [diff] [blame] | 170 | pl011_set_line_control(regs); |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 171 | /* Finally, enable the UART */ |
| 172 | writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | |
| 173 | UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr); |
| 174 | break; |
| 175 | } |
| 176 | default: |
| 177 | return -EINVAL; |
| 178 | } |
| 179 | |
| 180 | return 0; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 181 | } |
| 182 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 183 | #ifndef CONFIG_DM_SERIAL |
| 184 | static void pl01x_serial_init_baud(int baudrate) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 185 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 186 | int clock = 0; |
| 187 | |
| 188 | #if defined(CONFIG_PL010_SERIAL) |
| 189 | pl01x_type = TYPE_PL010; |
| 190 | #elif defined(CONFIG_PL011_SERIAL) |
| 191 | pl01x_type = TYPE_PL011; |
| 192 | clock = CONFIG_PL011_CLOCK; |
| 193 | #endif |
| 194 | base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX]; |
| 195 | |
| 196 | pl01x_generic_serial_init(base_regs, pl01x_type); |
Vikas Manocha | aac2396 | 2014-11-21 10:34:19 -0800 | [diff] [blame] | 197 | pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 198 | } |
| 199 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 200 | /* |
| 201 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 |
| 202 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 |
| 203 | * Versatile PB has four UARTs. |
| 204 | */ |
| 205 | int pl01x_serial_init(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 206 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 207 | pl01x_serial_init_baud(CONFIG_BAUDRATE); |
Linus Walleij | b8058e8 | 2011-10-02 11:52:52 +0000 | [diff] [blame] | 208 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 209 | return 0; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 210 | } |
| 211 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 212 | static void pl01x_serial_putc(const char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 213 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 214 | if (c == '\n') |
| 215 | while (pl01x_putc(base_regs, '\r') == -EAGAIN); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 216 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 217 | while (pl01x_putc(base_regs, c) == -EAGAIN); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 218 | } |
| 219 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 220 | static int pl01x_serial_getc(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 221 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 222 | while (1) { |
| 223 | int ch = pl01x_getc(base_regs); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 224 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 225 | if (ch == -EAGAIN) { |
| 226 | WATCHDOG_RESET(); |
| 227 | continue; |
| 228 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 229 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 230 | return ch; |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 231 | } |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 232 | } |
| 233 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 234 | static int pl01x_serial_tstc(void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 235 | { |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 236 | return pl01x_tstc(base_regs); |
| 237 | } |
Rabin Vincent | fb3c95f | 2010-05-05 09:23:07 +0530 | [diff] [blame] | 238 | |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 239 | static void pl01x_serial_setbrg(void) |
| 240 | { |
| 241 | /* |
| 242 | * Flush FIFO and wait for non-busy before changing baudrate to avoid |
| 243 | * crap in console |
| 244 | */ |
| 245 | while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE)) |
| 246 | WATCHDOG_RESET(); |
| 247 | while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY) |
| 248 | WATCHDOG_RESET(); |
| 249 | pl01x_serial_init_baud(gd->baudrate); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 250 | } |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 251 | |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 252 | static struct serial_device pl01x_serial_drv = { |
| 253 | .name = "pl01x_serial", |
| 254 | .start = pl01x_serial_init, |
| 255 | .stop = NULL, |
| 256 | .setbrg = pl01x_serial_setbrg, |
| 257 | .putc = pl01x_serial_putc, |
Marek Vasut | d9c6449 | 2012-10-06 14:07:02 +0000 | [diff] [blame] | 258 | .puts = default_serial_puts, |
Marek Vasut | 46e4d5f | 2012-09-14 22:38:46 +0200 | [diff] [blame] | 259 | .getc = pl01x_serial_getc, |
| 260 | .tstc = pl01x_serial_tstc, |
| 261 | }; |
| 262 | |
| 263 | void pl01x_serial_initialize(void) |
| 264 | { |
| 265 | serial_register(&pl01x_serial_drv); |
| 266 | } |
| 267 | |
| 268 | __weak struct serial_device *default_serial_console(void) |
| 269 | { |
| 270 | return &pl01x_serial_drv; |
| 271 | } |
Simon Glass | f35484d | 2014-09-22 17:30:57 -0600 | [diff] [blame] | 272 | |
| 273 | #endif /* nCONFIG_DM_SERIAL */ |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 274 | |
| 275 | #ifdef CONFIG_DM_SERIAL |
| 276 | |
| 277 | struct pl01x_priv { |
| 278 | struct pl01x_regs *regs; |
| 279 | enum pl01x_type type; |
| 280 | }; |
| 281 | |
| 282 | static int pl01x_serial_setbrg(struct udevice *dev, int baudrate) |
| 283 | { |
| 284 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
| 285 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 286 | |
Eric Anholt | be5a7dd | 2016-03-13 18:16:54 -0700 | [diff] [blame] | 287 | if (!plat->skip_init) { |
| 288 | pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, |
| 289 | baudrate); |
| 290 | } |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
| 295 | static int pl01x_serial_probe(struct udevice *dev) |
| 296 | { |
| 297 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
| 298 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 299 | |
| 300 | priv->regs = (struct pl01x_regs *)plat->base; |
| 301 | priv->type = plat->type; |
Eric Anholt | be5a7dd | 2016-03-13 18:16:54 -0700 | [diff] [blame] | 302 | if (!plat->skip_init) |
| 303 | return pl01x_generic_serial_init(priv->regs, priv->type); |
| 304 | else |
| 305 | return 0; |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | static int pl01x_serial_getc(struct udevice *dev) |
| 309 | { |
| 310 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 311 | |
| 312 | return pl01x_getc(priv->regs); |
| 313 | } |
| 314 | |
| 315 | static int pl01x_serial_putc(struct udevice *dev, const char ch) |
| 316 | { |
| 317 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 318 | |
| 319 | return pl01x_putc(priv->regs, ch); |
| 320 | } |
| 321 | |
| 322 | static int pl01x_serial_pending(struct udevice *dev, bool input) |
| 323 | { |
| 324 | struct pl01x_priv *priv = dev_get_priv(dev); |
| 325 | unsigned int fr = readl(&priv->regs->fr); |
| 326 | |
| 327 | if (input) |
| 328 | return pl01x_tstc(priv->regs); |
| 329 | else |
| 330 | return fr & UART_PL01x_FR_TXFF ? 0 : 1; |
| 331 | } |
| 332 | |
| 333 | static const struct dm_serial_ops pl01x_serial_ops = { |
| 334 | .putc = pl01x_serial_putc, |
| 335 | .pending = pl01x_serial_pending, |
| 336 | .getc = pl01x_serial_getc, |
| 337 | .setbrg = pl01x_serial_setbrg, |
| 338 | }; |
| 339 | |
Masahiro Yamada | 366b24f | 2015-08-12 07:31:55 +0900 | [diff] [blame] | 340 | #if CONFIG_IS_ENABLED(OF_CONTROL) |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 341 | static const struct udevice_id pl01x_serial_id[] ={ |
| 342 | {.compatible = "arm,pl011", .data = TYPE_PL011}, |
| 343 | {.compatible = "arm,pl010", .data = TYPE_PL010}, |
| 344 | {} |
| 345 | }; |
| 346 | |
| 347 | static int pl01x_serial_ofdata_to_platdata(struct udevice *dev) |
| 348 | { |
| 349 | struct pl01x_serial_platdata *plat = dev_get_platdata(dev); |
| 350 | fdt_addr_t addr; |
| 351 | |
Simon Glass | 0971778 | 2015-08-11 08:33:29 -0600 | [diff] [blame] | 352 | addr = dev_get_addr(dev); |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 353 | if (addr == FDT_ADDR_T_NONE) |
| 354 | return -EINVAL; |
| 355 | |
| 356 | plat->base = addr; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 357 | plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock", |
| 358 | 1); |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 359 | plat->type = dev_get_driver_data(dev); |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 360 | plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), |
Fabian Vogt | 7ca1f4e | 2016-09-26 14:26:45 +0200 | [diff] [blame] | 361 | "skip-init"); |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 362 | return 0; |
| 363 | } |
| 364 | #endif |
| 365 | |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 366 | U_BOOT_DRIVER(serial_pl01x) = { |
| 367 | .name = "serial_pl01x", |
| 368 | .id = UCLASS_SERIAL, |
Vikas Manocha | 92e349e | 2015-05-06 11:46:29 -0700 | [diff] [blame] | 369 | .of_match = of_match_ptr(pl01x_serial_id), |
| 370 | .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata), |
| 371 | .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 372 | .probe = pl01x_serial_probe, |
| 373 | .ops = &pl01x_serial_ops, |
| 374 | .flags = DM_FLAG_PRE_RELOC, |
Simon Glass | 900de91 | 2014-11-24 21:36:35 -0700 | [diff] [blame] | 375 | .priv_auto_alloc_size = sizeof(struct pl01x_priv), |
Simon Glass | 3ad93fe | 2014-09-22 17:30:58 -0600 | [diff] [blame] | 376 | }; |
| 377 | |
| 378 | #endif |
Sergey Temerkhanov | c0ffa4e | 2015-10-14 09:54:23 -0700 | [diff] [blame] | 379 | |
| 380 | #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) |
| 381 | |
| 382 | #include <debug_uart.h> |
| 383 | |
| 384 | static void _debug_uart_init(void) |
| 385 | { |
| 386 | #ifndef CONFIG_DEBUG_UART_SKIP_INIT |
| 387 | struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; |
| 388 | enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? |
| 389 | TYPE_PL011 : TYPE_PL010; |
| 390 | |
| 391 | pl01x_generic_serial_init(regs, type); |
| 392 | pl01x_generic_setbrg(regs, type, |
| 393 | CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); |
| 394 | #endif |
| 395 | } |
| 396 | |
| 397 | static inline void _debug_uart_putc(int ch) |
| 398 | { |
| 399 | struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; |
| 400 | |
| 401 | pl01x_putc(regs, ch); |
| 402 | } |
| 403 | |
| 404 | DEBUG_UART_FUNCS |
| 405 | |
| 406 | #endif |