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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Yand6e658c2017-06-01 18:01:31 +08002/*
3 * (C)Copyright 2016 Rockchip Electronics Co., Ltd
4 * Authors: Andy Yan <andy.yan@rock-chips.com>
Andy Yand6e658c2017-06-01 18:01:31 +08005 */
6
Simon Glass97589732020-05-10 11:40:02 -06007#include <init.h>
Kever Yangf6b6d942020-02-19 09:46:06 +08008#include <syscon.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Kever Yangf6b6d942020-02-19 09:46:06 +080010#include <asm/arch-rockchip/clock.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080011#include <asm/arch-rockchip/grf_rv1108.h>
12#include <asm/arch-rockchip/hardware.h>
Andy Yand6e658c2017-06-01 18:01:31 +080013
14DECLARE_GLOBAL_DATA_PTR;
15
Kever Yang8fdd8882020-04-13 09:38:30 +080016int board_early_init_f(void)
Andy Yand6e658c2017-06-01 18:01:31 +080017{
Andy Yand6e658c2017-06-01 18:01:31 +080018 struct rv1108_grf *grf;
David Wu5a04e0c2018-01-13 13:53:57 +080019 enum {
20 GPIO3C3_SHIFT = 6,
21 GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
22
23 GPIO3C2_SHIFT = 4,
24 GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
25
26 GPIO2D2_SHIFT = 4,
27 GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
28 GPIO2D2_GPIO = 0,
29 GPIO2D2_UART2_SOUT_M0,
30
31 GPIO2D1_SHIFT = 2,
32 GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
33 GPIO2D1_GPIO = 0,
34 GPIO2D1_UART2_SIN_M0,
35 };
Andy Yand6e658c2017-06-01 18:01:31 +080036
Kever Yangf6b6d942020-02-19 09:46:06 +080037 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
Andy Yand6e658c2017-06-01 18:01:31 +080038
39 /*evb board use UART2 m0 for debug*/
40 rk_clrsetreg(&grf->gpio2d_iomux,
41 GPIO2D2_MASK | GPIO2D1_MASK,
42 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
43 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
44 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
45
46 return 0;
47}
48
Andy Yand6e658c2017-06-01 18:01:31 +080049int dram_init(void)
50{
51 gd->ram_size = 0x8000000;
52
53 return 0;
54}