blob: fe37eac420f36d6fdc6519de2efe950b60234106 [file] [log] [blame]
Andy Yand6e658c2017-06-01 18:01:31 +08001/*
2 * (C)Copyright 2016 Rockchip Electronics Co., Ltd
3 * Authors: Andy Yan <andy.yan@rock-chips.com>
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <fdtdec.h>
10#include <asm/arch/grf_rv1108.h>
11#include <asm/arch/hardware.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15int mach_cpu_init(void)
16{
17 int node;
18 struct rv1108_grf *grf;
19
20 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf");
21 grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
22
23 /*evb board use UART2 m0 for debug*/
24 rk_clrsetreg(&grf->gpio2d_iomux,
25 GPIO2D2_MASK | GPIO2D1_MASK,
26 GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
27 GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
28 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK);
29
30 return 0;
31}
32
33
34int board_init(void)
35{
36 return 0;
37}
38
39int dram_init(void)
40{
41 gd->ram_size = 0x8000000;
42
43 return 0;
44}
45
46int dram_init_banksize(void)
47{
48 gd->bd->bi_dram[0].start = 0x60000000;
49 gd->bd->bi_dram[0].size = 0x8000000;
50
51 return 0;
52}