blob: e0b36f869a9cc68051c8686ef308a30b137c871f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Gala95bb67f2008-01-16 22:33:22 -06002/*
Kumar Galad7ff6a82011-02-03 20:21:42 -06003 * Copyright 2008-2011 Freescale Semiconductor, Inc.
Kumar Gala95bb67f2008-01-16 22:33:22 -06004 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Kumar Gala95bb67f2008-01-16 22:33:22 -06007 */
8
Tom Rinidec7ea02024-05-20 13:35:03 -06009#include <config.h>
Simon Glass1ab16922022-07-31 12:28:48 -060010#include <display_options.h>
Ovidiu Panait7dbb0212022-01-01 19:13:29 +020011#include <init.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060012#include <asm/bitops.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Kumar Gala95bb67f2008-01-16 22:33:22 -060014#include <asm/processor.h>
15#include <asm/mmu.h>
Kumar Gala9ac287a2008-12-16 14:59:20 -060016#ifdef CONFIG_ADDR_MAP
17#include <addr_map.h>
18#endif
19
Fabio Estevam1a03a7e2015-11-05 12:43:40 -020020#include <linux/log2.h>
21
Kumar Gala9ac287a2008-12-16 14:59:20 -060022DECLARE_GLOBAL_DATA_PTR;
Kumar Gala95bb67f2008-01-16 22:33:22 -060023
Kumar Galaafc51ad2009-09-11 12:32:01 -050024void invalidate_tlb(u8 tlb)
25{
26 if (tlb == 0)
27 mtspr(MMUCSR0, 0x4);
28 if (tlb == 1)
29 mtspr(MMUCSR0, 0x2);
30}
31
Alexander Grafc3468482014-04-11 17:09:45 +020032__weak void init_tlbs(void)
Kumar Galaafc51ad2009-09-11 12:32:01 -050033{
34 int i;
35
36 for (i = 0; i < num_tlb_entries; i++) {
37 write_tlb(tlb_table[i].mas0,
38 tlb_table[i].mas1,
39 tlb_table[i].mas2,
40 tlb_table[i].mas3,
41 tlb_table[i].mas7);
42 }
43
Bin Meng75a6a372022-10-26 12:40:07 +080044 return;
Kumar Galaafc51ad2009-09-11 12:32:01 -050045}
46
Ying Zhangffc86e22013-08-16 15:16:10 +080047#if !defined(CONFIG_NAND_SPL) && \
Tom Rini6b15c162022-05-13 12:26:35 -040048 (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
Becky Bruce9fa52d42010-06-17 11:37:21 -050049void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
50 phys_addr_t *rpn)
51{
52 u32 _mas1;
53
54 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
55 asm volatile("tlbre;isync");
56 _mas1 = mfspr(MAS1);
57
58 *valid = (_mas1 & MAS1_VALID);
Scott Wood33a619c2013-01-18 15:45:58 +000059 *tsize = (_mas1 >> 7) & 0x1f;
Becky Bruce9fa52d42010-06-17 11:37:21 -050060 *epn = mfspr(MAS2) & MAS2_EPN;
61 *rpn = mfspr(MAS3) & MAS3_RPN;
62#ifdef CONFIG_ENABLE_36BIT_PHYS
63 *rpn |= ((u64)mfspr(MAS7)) << 32;
64#endif
65}
66
Becky Bruce7b9cdb42010-06-17 11:37:22 -050067void print_tlbcam(void)
68{
69 int i;
70 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
71
72 /* walk all the entries */
73 printf("TLBCAM entries\n");
74 for (i = 0; i < num_cam; i++) {
75 unsigned long epn;
76 u32 tsize, valid;
77 phys_addr_t rpn;
78
79 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
80 printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
81 i, (valid == 0) ? 0 : 1, (unsigned int)epn,
82 (unsigned long long)rpn);
83 print_size(TSIZE_TO_BYTES(tsize), "\n");
84 }
85}
86
Kumar Gala42f99182009-11-12 10:26:16 -060087static inline void use_tlb_cam(u8 idx)
88{
89 int i = idx / 32;
90 int bit = idx % 32;
91
Simon Glass0b466582012-12-13 20:48:52 +000092 gd->arch.used_tlb_cams[i] |= (1 << bit);
Kumar Gala42f99182009-11-12 10:26:16 -060093}
94
95static inline void free_tlb_cam(u8 idx)
96{
97 int i = idx / 32;
98 int bit = idx % 32;
99
Simon Glass0b466582012-12-13 20:48:52 +0000100 gd->arch.used_tlb_cams[i] &= ~(1 << bit);
Kumar Gala42f99182009-11-12 10:26:16 -0600101}
102
103void init_used_tlb_cams(void)
104{
105 int i;
106 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
107
108 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
Simon Glass0b466582012-12-13 20:48:52 +0000109 gd->arch.used_tlb_cams[i] = 0;
Kumar Gala42f99182009-11-12 10:26:16 -0600110
111 /* walk all the entries */
112 for (i = 0; i < num_cam; i++) {
Kumar Gala42f99182009-11-12 10:26:16 -0600113 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
Kumar Gala42f99182009-11-12 10:26:16 -0600114 asm volatile("tlbre;isync");
Becky Bruce9fa52d42010-06-17 11:37:21 -0500115 if (mfspr(MAS1) & MAS1_VALID)
Kumar Gala42f99182009-11-12 10:26:16 -0600116 use_tlb_cam(i);
117 }
118}
119
120int find_free_tlbcam(void)
121{
122 int i;
123 u32 idx;
124
125 for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
Simon Glass0b466582012-12-13 20:48:52 +0000126 idx = ffz(gd->arch.used_tlb_cams[i]);
Kumar Gala42f99182009-11-12 10:26:16 -0600127
128 if (idx != 32)
129 break;
130 }
131
132 idx += i * 32;
133
134 if (idx >= CONFIG_SYS_NUM_TLBCAMS)
135 return -1;
136
137 return idx;
138}
139
Kumar Gala95bb67f2008-01-16 22:33:22 -0600140void set_tlb(u8 tlb, u32 epn, u64 rpn,
141 u8 perms, u8 wimge,
142 u8 ts, u8 esel, u8 tsize, u8 iprot)
143{
144 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
145
Kumar Gala42f99182009-11-12 10:26:16 -0600146 if (tlb == 1)
147 use_tlb_cam(esel);
148
Scott Wood33a619c2013-01-18 15:45:58 +0000149 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
150 tsize & 1) {
151 printf("%s: bad tsize %d on entry %d at 0x%08x\n",
152 __func__, tsize, tlb, epn);
153 return;
154 }
155
Kumar Gala95bb67f2008-01-16 22:33:22 -0600156 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
157 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
158 _mas2 = FSL_BOOKE_MAS2(epn, wimge);
159 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
Kumar Galac417c912009-09-11 11:27:00 -0500160 _mas7 = FSL_BOOKE_MAS7(rpn);
Kumar Gala95bb67f2008-01-16 22:33:22 -0600161
Kumar Galac417c912009-09-11 11:27:00 -0500162 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
Kumar Gala9ac287a2008-12-16 14:59:20 -0600163
164#ifdef CONFIG_ADDR_MAP
165 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
Becky Bruce9fa52d42010-06-17 11:37:21 -0500166 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
Kumar Gala9ac287a2008-12-16 14:59:20 -0600167#endif
Kumar Gala95bb67f2008-01-16 22:33:22 -0600168}
169
170void disable_tlb(u8 esel)
171{
Kumar Gala4a272472011-11-09 09:59:32 -0600172 u32 _mas0, _mas1, _mas2, _mas3;
Kumar Gala95bb67f2008-01-16 22:33:22 -0600173
Kumar Gala42f99182009-11-12 10:26:16 -0600174 free_tlb_cam(esel);
175
Kumar Gala95bb67f2008-01-16 22:33:22 -0600176 _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
177 _mas1 = 0;
178 _mas2 = 0;
179 _mas3 = 0;
Kumar Gala95bb67f2008-01-16 22:33:22 -0600180
181 mtspr(MAS0, _mas0);
182 mtspr(MAS1, _mas1);
183 mtspr(MAS2, _mas2);
184 mtspr(MAS3, _mas3);
185#ifdef CONFIG_ENABLE_36BIT_PHYS
Kumar Gala4a272472011-11-09 09:59:32 -0600186 mtspr(MAS7, 0);
Kumar Gala95bb67f2008-01-16 22:33:22 -0600187#endif
188 asm volatile("isync;msync;tlbwe;isync");
Kumar Gala9ac287a2008-12-16 14:59:20 -0600189
190#ifdef CONFIG_ADDR_MAP
191 if (gd->flags & GD_FLG_RELOC)
192 addrmap_set_entry(0, 0, 0, esel);
193#endif
Kumar Gala95bb67f2008-01-16 22:33:22 -0600194}
195
Kumar Galad13eb3c2009-09-03 08:20:24 -0500196static void tlbsx (const volatile unsigned *addr)
197{
198 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
199}
200
201/* return -1 if we didn't find anything */
202int find_tlb_idx(void *addr, u8 tlbsel)
203{
204 u32 _mas0, _mas1;
205
206 /* zero out Search PID, AS */
207 mtspr(MAS6, 0);
208
209 tlbsx(addr);
210
211 _mas0 = mfspr(MAS0);
212 _mas1 = mfspr(MAS1);
213
214 /* we found something, and its in the TLB we expect */
215 if ((MAS1_VALID & _mas1) &&
216 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
217 return ((_mas0 & MAS0_ESEL_MSK) >> 16);
218 }
219
220 return -1;
221}
222
Kumar Gala9ac287a2008-12-16 14:59:20 -0600223#ifdef CONFIG_ADDR_MAP
Ovidiu Panait9ef3c8a2022-01-01 19:13:28 +0200224int init_addr_map(void)
Kumar Gala9ac287a2008-12-16 14:59:20 -0600225{
226 int i;
Kumar Gala7601fb22009-11-13 08:52:21 -0600227 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
Kumar Gala9ac287a2008-12-16 14:59:20 -0600228
Kumar Gala87f57922009-08-14 16:43:22 -0500229 /* walk all the entries */
Kumar Gala7601fb22009-11-13 08:52:21 -0600230 for (i = 0; i < num_cam; i++) {
Kumar Gala87f57922009-08-14 16:43:22 -0500231 unsigned long epn;
Becky Bruce9fa52d42010-06-17 11:37:21 -0500232 u32 tsize, valid;
Kumar Gala87f57922009-08-14 16:43:22 -0500233 phys_addr_t rpn;
234
Becky Bruce9fa52d42010-06-17 11:37:21 -0500235 read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
236 if (valid & MAS1_VALID)
237 addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
Kumar Gala9ac287a2008-12-16 14:59:20 -0600238 }
239
Ovidiu Panait9ef3c8a2022-01-01 19:13:28 +0200240 return 0;
Kumar Gala9ac287a2008-12-16 14:59:20 -0600241}
242#endif
243
Alexander Graf4c5d4262014-04-11 17:09:43 +0200244uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
245 enum tlb_map_type map_type)
Kumar Gala80f4bc72008-06-09 11:07:46 -0500246{
Kumar Gala419083b2009-11-13 09:04:19 -0600247 int i;
Kumar Gala80f4bc72008-06-09 11:07:46 -0500248 unsigned int tlb_size;
Alexander Graf4c5d4262014-04-11 17:09:43 +0200249 unsigned int wimge;
250 unsigned int perm;
Scott Wood33a619c2013-01-18 15:45:58 +0000251 unsigned int max_cam, tsize_mask;
Kumar Gala80f4bc72008-06-09 11:07:46 -0500252
Alexander Graf4c5d4262014-04-11 17:09:43 +0200253 if (map_type == TLB_MAP_RAM) {
254 perm = MAS3_SX|MAS3_SW|MAS3_SR;
255 wimge = MAS2_M;
Becky Bruce92e163f2010-12-17 17:17:55 -0600256#ifdef CONFIG_SYS_PPC_DDR_WIMGE
Alexander Graf4c5d4262014-04-11 17:09:43 +0200257 wimge = CONFIG_SYS_PPC_DDR_WIMGE;
Becky Bruce92e163f2010-12-17 17:17:55 -0600258#endif
Alexander Graf4c5d4262014-04-11 17:09:43 +0200259 } else {
260 perm = MAS3_SW|MAS3_SR;
261 wimge = MAS2_I|MAS2_G;
262 }
263
Kumar Galaac7e8952011-10-31 22:13:26 -0500264 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
265 /* Convert (4^max) kB to (2^max) bytes */
266 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
Scott Wood33a619c2013-01-18 15:45:58 +0000267 tsize_mask = ~1U;
Kumar Galaac7e8952011-10-31 22:13:26 -0500268 } else {
269 /* Convert (2^max) kB to (2^max) bytes */
270 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
Scott Wood33a619c2013-01-18 15:45:58 +0000271 tsize_mask = ~0U;
Kumar Galaac7e8952011-10-31 22:13:26 -0500272 }
Kumar Gala6630ffb2009-02-06 09:56:35 -0600273
Kumar Gala419083b2009-11-13 09:04:19 -0600274 for (i = 0; size && i < 8; i++) {
Alexander Graf4c5d4262014-04-11 17:09:43 +0200275 int tlb_index = find_free_tlbcam();
Scott Wood33a619c2013-01-18 15:45:58 +0000276 u32 camsize = __ilog2_u64(size) & tsize_mask;
Alexander Graf4c5d4262014-04-11 17:09:43 +0200277 u32 align = __ilog2(v_addr) & tsize_mask;
Kumar Gala6630ffb2009-02-06 09:56:35 -0600278
Alexander Graf4c5d4262014-04-11 17:09:43 +0200279 if (tlb_index == -1)
Kumar Gala419083b2009-11-13 09:04:19 -0600280 break;
281
Kumar Gala6630ffb2009-02-06 09:56:35 -0600282 if (align == -2) align = max_cam;
283 if (camsize > align)
284 camsize = align;
Kumar Gala80f4bc72008-06-09 11:07:46 -0500285
Kumar Gala6630ffb2009-02-06 09:56:35 -0600286 if (camsize > max_cam)
287 camsize = max_cam;
288
Scott Wood33a619c2013-01-18 15:45:58 +0000289 tlb_size = camsize - 10;
Kumar Gala6630ffb2009-02-06 09:56:35 -0600290
Alexander Graf4c5d4262014-04-11 17:09:43 +0200291 set_tlb(1, v_addr, p_addr, perm, wimge,
292 0, tlb_index, tlb_size, 1);
Kumar Gala80f4bc72008-06-09 11:07:46 -0500293
Kumar Gala6630ffb2009-02-06 09:56:35 -0600294 size -= 1ULL << camsize;
Alexander Graf4c5d4262014-04-11 17:09:43 +0200295 v_addr += 1UL << camsize;
York Sunba99a332010-09-28 15:20:32 -0700296 p_addr += 1UL << camsize;
Kumar Gala80f4bc72008-06-09 11:07:46 -0500297 }
298
Alexander Graf4c5d4262014-04-11 17:09:43 +0200299 return size;
300}
301
302unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
303 unsigned int memsize_in_meg)
304{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500305 unsigned int ram_tlb_address = (unsigned int)CFG_SYS_DDR_SDRAM_BASE;
Alexander Graf4c5d4262014-04-11 17:09:43 +0200306 u64 memsize = (u64)memsize_in_meg << 20;
York Sun55ec4812014-12-02 11:21:09 -0800307 u64 size;
Alexander Graf4c5d4262014-04-11 17:09:43 +0200308
Tom Rinibc9d46b2022-12-04 10:04:50 -0500309 size = min(memsize, (u64)CFG_MAX_MEM_MAPPED);
York Sun55ec4812014-12-02 11:21:09 -0800310 size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
Alexander Graf4c5d4262014-04-11 17:09:43 +0200311
Tom Rinibc9d46b2022-12-04 10:04:50 -0500312 if (size || memsize > CFG_MAX_MEM_MAPPED) {
313 print_size(memsize > CFG_MAX_MEM_MAPPED ?
314 memsize - CFG_MAX_MEM_MAPPED + size : size,
Pali Rohár777ba482022-09-09 17:32:46 +0200315 " of DDR memory left unmapped in U-Boot\n");
Pali Rohár16f862f2022-09-11 11:29:16 +0200316#ifndef CONFIG_SPL_BUILD
317 puts(" ");
318#endif
York Sun55ec4812014-12-02 11:21:09 -0800319 }
Alexander Graf4c5d4262014-04-11 17:09:43 +0200320
Kumar Gala80f4bc72008-06-09 11:07:46 -0500321 return memsize_in_meg;
322}
York Sunba99a332010-09-28 15:20:32 -0700323
324unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
325{
326 return
Tom Rini6a5dccc2022-11-16 13:10:41 -0500327 setup_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
York Sunba99a332010-09-28 15:20:32 -0700328}
Becky Bruce69694472011-07-18 18:49:15 -0500329
330/* Invalidate the DDR TLBs for the requested size */
331void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
332{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500333 u32 vstart = CFG_SYS_DDR_SDRAM_BASE;
Becky Bruce69694472011-07-18 18:49:15 -0500334 unsigned long epn;
335 u32 tsize, valid, ptr;
336 phys_addr_t rpn = 0;
337 int ddr_esel;
338 u64 memsize = (u64)memsize_in_meg << 20;
339
340 ptr = vstart;
341
342 while (ptr < (vstart + memsize)) {
343 ddr_esel = find_tlb_idx((void *)ptr, 1);
344 if (ddr_esel != -1) {
345 read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
346 disable_tlb(ddr_esel);
347 }
348 ptr += TSIZE_TO_BYTES(tsize);
349 }
350}
351
352void clear_ddr_tlbs(unsigned int memsize_in_meg)
353{
Tom Rini6a5dccc2022-11-16 13:10:41 -0500354 clear_ddr_tlbs_phys(CFG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
Becky Bruce69694472011-07-18 18:49:15 -0500355}
356
357
Scott Wood095b7122012-09-20 19:02:18 -0500358#endif /* not SPL */