| commit | 419083bc1ee7be7bf7d853311104651962b7ce28 | [log] [tgz] |
|---|---|---|
| author | Kumar Gala <galak@kernel.crashing.org> | Fri Nov 13 09:04:19 2009 -0600 |
| committer | Kumar Gala <galak@kernel.crashing.org> | Tue Jan 05 13:49:08 2010 -0600 |
| tree | 7380c8c9cd3d6464f0da09767b7fcd3ccf41c06a | |
| parent | 42f99184d9f2c625cad64ee6333b311a43ba7bd0 [diff] |
ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocation Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>