blob: e847c03f378b4135b2bd72fca720eeb2e0863998 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
Dave Liub19ecd32007-09-18 12:37:57 +08003 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
Dave Liuf5035922006-10-25 14:41:21 -05004 *
Rafal Jaworowski4a9b6aa2006-03-16 17:46:46 +01005 * (C) Copyright 2006
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkebd3deb2006-04-16 10:51:58 +02007 *
Dave Liua46daea2006-11-03 19:33:44 -06008 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05009 * (C) Copyright 2003 Motorola Inc.
10 * Xianghua Xiao (X.Xiao@motorola.com)
Eran Liberty9095d4a2005-07-28 10:08:46 -050011 */
12
Mario Six538b5752018-08-06 10:23:30 +020013#ifndef CONFIG_MPC83XX_SDRAM
14
Simon Glass1d91ba72019-11-14 12:57:37 -070015#include <cpu_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Simon Glassa9dc0682019-12-28 10:44:59 -070017#include <time.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070018#include <vsprintf.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050019#include <asm/processor.h>
Stefan Roese3fab9992009-12-08 09:10:04 +010020#include <asm/io.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050021#include <i2c.h>
22#include <spd.h>
23#include <asm/mmu.h>
24#include <spd_sdram.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060025#include <asm/bitops.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060026#include <asm/global_data.h>
Simon Glassdbd79542020-05-10 11:40:11 -060027#include <linux/delay.h>
Eran Liberty9095d4a2005-07-28 10:08:46 -050028
Kim Phillipsdf6df6f2008-03-28 10:18:53 -050029DECLARE_GLOBAL_DATA_PTR;
30
Kim Phillips3b9c20f2007-08-16 22:52:48 -050031void board_add_ram_info(int use_default)
32{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020033 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Kim Phillips3b9c20f2007-08-16 22:52:48 -050034 volatile ddr83xx_t *ddr = &immap->ddr;
Kim Phillipsdf6df6f2008-03-28 10:18:53 -050035 char buf[32];
Kim Phillips3b9c20f2007-08-16 22:52:48 -050036
37 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
38 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
39
Mario Six9164bdd2019-01-21 09:17:25 +010040#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
Joe Hershbergercc03b802011-10-11 23:57:29 -050041 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
42 puts(", 16-bit");
43 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
44 puts(", 32-bit");
45 else
46 puts(", unknown width");
47#else
Kim Phillips3b9c20f2007-08-16 22:52:48 -050048 if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
49 puts(", 32-bit");
50 else
51 puts(", 64-bit");
Joe Hershbergercc03b802011-10-11 23:57:29 -050052#endif
Kim Phillips3b9c20f2007-08-16 22:52:48 -050053
54 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
Kim Phillipsdf6df6f2008-03-28 10:18:53 -050055 puts(", ECC on");
Kim Phillips3b9c20f2007-08-16 22:52:48 -050056 else
Kim Phillipsdf6df6f2008-03-28 10:18:53 -050057 puts(", ECC off");
58
59 printf(", %s MHz)", strmhz(buf, gd->mem_clk));
Kim Phillips3b9c20f2007-08-16 22:52:48 -050060
Tom Rini6a5dccc2022-11-16 13:10:41 -050061#if defined(CONFIG_SYS_LB_SDRAM) && defined(CFG_SYS_LBC_SDRAM_SIZE)
Kim Phillips3b9c20f2007-08-16 22:52:48 -050062 puts("\nSDRAM: ");
Tom Rini6a5dccc2022-11-16 13:10:41 -050063 print_size (CFG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
Kim Phillips3b9c20f2007-08-16 22:52:48 -050064#endif
65}
66
Eran Liberty9095d4a2005-07-28 10:08:46 -050067#ifdef CONFIG_SPD_EEPROM
Tom Rini364d0022023-01-10 11:19:45 -050068#ifndef CFG_SYS_READ_SPD
69#define CFG_SYS_READ_SPD i2c_read
Eran Liberty9095d4a2005-07-28 10:08:46 -050070#endif
Andre Schwarz10ea0af2011-04-14 14:54:05 +020071#ifndef SPD_EEPROM_OFFSET
72#define SPD_EEPROM_OFFSET 0
73#endif
74#ifndef SPD_EEPROM_ADDR_LEN
75#define SPD_EEPROM_ADDR_LEN 1
76#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050077
Eran Liberty9095d4a2005-07-28 10:08:46 -050078/*
79 * Convert picoseconds into clock cycles (rounding up if needed).
80 */
Eran Liberty9095d4a2005-07-28 10:08:46 -050081int
82picos_to_clk(int picos)
83{
Kim Phillipsc02cf1e2008-03-28 10:18:40 -050084 unsigned int mem_bus_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050085 int clks;
86
Kim Phillipsc02cf1e2008-03-28 10:18:40 -050087 mem_bus_clk = gd->mem_clk >> 1;
88 clks = picos / (1000000000 / (mem_bus_clk / 1000));
89 if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
Dave Liuf5035922006-10-25 14:41:21 -050090 clks++;
Eran Liberty9095d4a2005-07-28 10:08:46 -050091
92 return clks;
93}
94
Marian Balakowicz6f6104d2006-03-14 16:23:35 +010095unsigned int banksize(unsigned char row_dens)
Eran Liberty9095d4a2005-07-28 10:08:46 -050096{
97 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
98}
99
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100100int read_spd(uint addr)
101{
102 return ((int) addr);
103}
104
Rafal Jaworowski4a9b6aa2006-03-16 17:46:46 +0100105#undef SPD_DEBUG
106#ifdef SPD_DEBUG
107static void spd_debug(spd_eeprom_t *spd)
108{
109 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
110 printf ("SPD size: %d\n", spd->info_size);
111 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
112 printf ("Memory type: %d\n", spd->mem_type);
113 printf ("Row addr: %d\n", spd->nrow_addr);
114 printf ("Column addr: %d\n", spd->ncol_addr);
115 printf ("# of rows: %d\n", spd->nrows);
116 printf ("Row density: %d\n", spd->row_dens);
117 printf ("# of banks: %d\n", spd->nbanks);
118 printf ("Data width: %d\n",
119 256 * spd->dataw_msb + spd->dataw_lsb);
120 printf ("Chip width: %d\n", spd->primw);
121 printf ("Refresh rate: %02X\n", spd->refresh);
122 printf ("CAS latencies: %02X\n", spd->cas_lat);
123 printf ("Write latencies: %02X\n", spd->write_lat);
124 printf ("tRP: %d\n", spd->trp);
125 printf ("tRCD: %d\n", spd->trcd);
126 printf ("\n");
127}
128#endif /* SPD_DEBUG */
129
130long int spd_sdram()
Eran Liberty9095d4a2005-07-28 10:08:46 -0500131{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf5035922006-10-25 14:41:21 -0500133 volatile ddr83xx_t *ddr = &immap->ddr;
134 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
Eran Liberty9095d4a2005-07-28 10:08:46 -0500135 spd_eeprom_t spd;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800136 unsigned int n_ranks;
137 unsigned int odt_rd_cfg, odt_wr_cfg;
138 unsigned char twr_clk, twtr_clk;
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500139 unsigned int sdram_type;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500140 unsigned int memsize;
141 unsigned int law_size;
Dave Liuf5035922006-10-25 14:41:21 -0500142 unsigned char caslat, caslat_ctrl;
Kim Phillips805b3c62011-11-15 22:59:51 +0000143 unsigned int trfc, trfc_clk, trfc_low;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800144 unsigned int trcd_clk, trtp_clk;
145 unsigned char cke_min_clk;
146 unsigned char add_lat, wr_lat;
147 unsigned char wr_data_delay;
148 unsigned char four_act;
149 unsigned char cpo;
Dave Liuf5035922006-10-25 14:41:21 -0500150 unsigned char burstlen;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800151 unsigned char odt_cfg, mode_odt_enable;
Dave Liuf5035922006-10-25 14:41:21 -0500152 unsigned int max_bus_clk;
153 unsigned int max_data_rate, effective_data_rate;
154 unsigned int ddrc_clk;
155 unsigned int refresh_clk;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800156 unsigned int sdram_cfg;
Dave Liuf5035922006-10-25 14:41:21 -0500157 unsigned int ddrc_ecc_enable;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800158 unsigned int pvr = get_pvr();
Jon Loeligerebc72242005-08-01 13:20:47 -0500159
Stefan Roese3fab9992009-12-08 09:10:04 +0100160 /*
161 * First disable the memory controller (could be enabled
162 * by the debugger)
163 */
164 clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
165 sync();
166 isync();
167
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100168 /* Read SPD parameters with I2C */
Tom Rini364d0022023-01-10 11:19:45 -0500169 CFG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
Andre Schwarz10ea0af2011-04-14 14:54:05 +0200170 SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
Rafal Jaworowski4a9b6aa2006-03-16 17:46:46 +0100171#ifdef SPD_DEBUG
172 spd_debug(&spd);
173#endif
Dave Liuf5035922006-10-25 14:41:21 -0500174 /* Check the memory type */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800175 if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500176 debug("DDR: Module mem type is %02X\n", spd.mem_type);
Dave Liuf5035922006-10-25 14:41:21 -0500177 return 0;
178 }
179
180 /* Check the number of physical bank */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800181 if (spd.mem_type == SPD_MEMTYPE_DDR) {
182 n_ranks = spd.nrows;
183 } else {
184 n_ranks = (spd.nrows & 0x7) + 1;
185 }
186
187 if (n_ranks > 2) {
188 printf("DDR: The number of physical bank is %02X\n", n_ranks);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500189 return 0;
190 }
191
Dave Liuf5035922006-10-25 14:41:21 -0500192 /* Check if the number of row of the module is in the range of DDRC */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800193 if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
Dave Liuf5035922006-10-25 14:41:21 -0500194 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
195 spd.nrow_addr);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500196 return 0;
197 }
198
Dave Liuf5035922006-10-25 14:41:21 -0500199 /* Check if the number of col of the module is in the range of DDRC */
200 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
201 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
202 spd.ncol_addr);
203 return 0;
204 }
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800205
Tom Rini6a5dccc2022-11-16 13:10:41 -0500206#ifdef CFG_SYS_DDRCDR_VALUE
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800207 /*
208 * Adjust DDR II IO voltage biasing. It just makes it work.
209 */
210 if(spd.mem_type == SPD_MEMTYPE_DDR2) {
Tom Rini6a5dccc2022-11-16 13:10:41 -0500211 immap->sysconf.ddrcdr = CFG_SYS_DDRCDR_VALUE;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800212 }
Dave Liub19ecd32007-09-18 12:37:57 +0800213 udelay(50000);
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800214#endif
215
216 /*
217 * ODT configuration recommendation from DDR Controller Chapter.
218 */
219 odt_rd_cfg = 0; /* Never assert ODT */
220 odt_wr_cfg = 0; /* Never assert ODT */
221 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
222 odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
223 }
224
Wolfgang Denk87b3d4b2006-11-30 18:02:20 +0100225 /* Setup DDR chip select register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200226#ifdef CONFIG_SYS_83XX_DDR_USES_CS0
Dave Liua46daea2006-11-03 19:33:44 -0600227 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
228 ddr->cs_config[0] = ( 1 << 31
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800229 | (odt_rd_cfg << 20)
230 | (odt_wr_cfg << 16)
Jerry Van Barena07888b2009-03-13 11:40:10 -0400231 | ((spd.nbanks == 8 ? 1 : 0) << 14)
232 | ((spd.nrow_addr - 12) << 8)
Dave Liua46daea2006-11-03 19:33:44 -0600233 | (spd.ncol_addr - 8) );
234 debug("\n");
235 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
236 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
237
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800238 if (n_ranks == 2) {
Dave Liua46daea2006-11-03 19:33:44 -0600239 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
240 | ((banksize(spd.row_dens) >> 23) - 1) );
241 ddr->cs_config[1] = ( 1<<31
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800242 | (odt_rd_cfg << 20)
243 | (odt_wr_cfg << 16)
Jerry Van Barena07888b2009-03-13 11:40:10 -0400244 | ((spd.nbanks == 8 ? 1 : 0) << 14)
245 | ((spd.nrow_addr - 12) << 8)
246 | (spd.ncol_addr - 8) );
Dave Liua46daea2006-11-03 19:33:44 -0600247 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
248 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
249 }
250
251#else
Eran Liberty9095d4a2005-07-28 10:08:46 -0500252 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
253 ddr->cs_config[2] = ( 1 << 31
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800254 | (odt_rd_cfg << 20)
255 | (odt_wr_cfg << 16)
Jerry Van Barena07888b2009-03-13 11:40:10 -0400256 | ((spd.nbanks == 8 ? 1 : 0) << 14)
257 | ((spd.nrow_addr - 12) << 8)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500258 | (spd.ncol_addr - 8) );
259 debug("\n");
260 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
261 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
Jon Loeligerebc72242005-08-01 13:20:47 -0500262
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800263 if (n_ranks == 2) {
Eran Liberty9095d4a2005-07-28 10:08:46 -0500264 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
265 | ((banksize(spd.row_dens) >> 23) - 1) );
266 ddr->cs_config[3] = ( 1<<31
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800267 | (odt_rd_cfg << 20)
268 | (odt_wr_cfg << 16)
Jerry Van Barena07888b2009-03-13 11:40:10 -0400269 | ((spd.nbanks == 8 ? 1 : 0) << 14)
270 | ((spd.nrow_addr - 12) << 8)
271 | (spd.ncol_addr - 8) );
Eran Liberty9095d4a2005-07-28 10:08:46 -0500272 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
273 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
274 }
Timur Tabi054838e2006-10-31 18:44:42 -0600275#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500276
Eran Liberty9095d4a2005-07-28 10:08:46 -0500277 /*
278 * Figure out memory size in Megabytes.
279 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800280 memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500281
282 /*
283 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
284 */
285 law_size = 19 + __ilog2(memsize);
286
287 /*
288 * Set up LAWBAR for all of DDR.
289 */
Tom Rinibb4dd962022-11-16 13:10:37 -0500290 ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500291 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
292 debug("DDR:bar=0x%08x\n", ecm->bar);
293 debug("DDR:ar=0x%08x\n", ecm->ar);
294
295 /*
Dave Liuf5035922006-10-25 14:41:21 -0500296 * Find the largest CAS by locating the highest 1 bit
297 * in the spd.cas_lat field. Translate it to a DDR
298 * controller field value:
299 *
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800300 * CAS Lat DDR I DDR II Ctrl
301 * Clocks SPD Bit SPD Bit Value
302 * ------- ------- ------- -----
303 * 1.0 0 0001
304 * 1.5 1 0010
305 * 2.0 2 2 0011
306 * 2.5 3 0100
307 * 3.0 4 3 0101
308 * 3.5 5 0110
309 * 4.0 6 4 0111
310 * 4.5 1000
311 * 5.0 5 1001
Eran Liberty9095d4a2005-07-28 10:08:46 -0500312 */
Dave Liuf5035922006-10-25 14:41:21 -0500313 caslat = __ilog2(spd.cas_lat);
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800314 if ((spd.mem_type == SPD_MEMTYPE_DDR)
315 && (caslat > 6)) {
316 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
317 return 0;
318 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
319 && (caslat < 2 || caslat > 5)) {
320 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
321 spd.cas_lat);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500322 return 0;
323 }
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800324 debug("DDR: caslat SPD bit is %d\n", caslat);
325
Dave Liuf5035922006-10-25 14:41:21 -0500326 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
327 + (spd.clk_cycle & 0x0f));
328 max_data_rate = max_bus_clk * 2;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500329
Wolfgang Denkaf0501a2008-10-19 02:35:50 +0200330 debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500331
Kim Phillipsc02cf1e2008-03-28 10:18:40 -0500332 ddrc_clk = gd->mem_clk / 1000000;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800333 effective_data_rate = 0;
Dave Liuf5035922006-10-25 14:41:21 -0500334
Dave Liu6b051042009-02-25 12:31:32 +0800335 if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
336 if (spd.cas_lat & 0x08)
337 caslat = 3;
338 else
339 caslat = 4;
340 if (ddrc_clk <= 460 && ddrc_clk > 350)
341 effective_data_rate = 400;
342 else if (ddrc_clk <=350 && ddrc_clk > 280)
343 effective_data_rate = 333;
344 else if (ddrc_clk <= 280 && ddrc_clk > 230)
345 effective_data_rate = 266;
346 else
347 effective_data_rate = 200;
348 } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800349 if (ddrc_clk <= 460 && ddrc_clk > 350) {
350 /* DDR controller clk at 350~460 */
Dave Liua46daea2006-11-03 19:33:44 -0600351 effective_data_rate = 400; /* 5ns */
352 caslat = caslat;
353 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
354 /* DDR controller clk at 280~350 */
355 effective_data_rate = 333; /* 6ns */
Timur Tabiff0215a2006-11-28 12:09:35 -0600356 if (spd.clk_cycle2 == 0x60)
Dave Liua46daea2006-11-03 19:33:44 -0600357 caslat = caslat - 1;
Timur Tabiff0215a2006-11-28 12:09:35 -0600358 else
Dave Liua46daea2006-11-03 19:33:44 -0600359 caslat = caslat;
Dave Liua46daea2006-11-03 19:33:44 -0600360 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
361 /* DDR controller clk at 230~280 */
362 effective_data_rate = 266; /* 7.5ns */
Timur Tabiff0215a2006-11-28 12:09:35 -0600363 if (spd.clk_cycle3 == 0x75)
Dave Liua46daea2006-11-03 19:33:44 -0600364 caslat = caslat - 2;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800365 else if (spd.clk_cycle2 == 0x75)
Dave Liua46daea2006-11-03 19:33:44 -0600366 caslat = caslat - 1;
Timur Tabiff0215a2006-11-28 12:09:35 -0600367 else
Dave Liua46daea2006-11-03 19:33:44 -0600368 caslat = caslat;
Dave Liua46daea2006-11-03 19:33:44 -0600369 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
370 /* DDR controller clk at 90~230 */
371 effective_data_rate = 200; /* 10ns */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800372 if (spd.clk_cycle3 == 0xa0)
Dave Liua46daea2006-11-03 19:33:44 -0600373 caslat = caslat - 2;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800374 else if (spd.clk_cycle2 == 0xa0)
Dave Liua46daea2006-11-03 19:33:44 -0600375 caslat = caslat - 1;
Timur Tabiff0215a2006-11-28 12:09:35 -0600376 else
Dave Liua46daea2006-11-03 19:33:44 -0600377 caslat = caslat;
Dave Liua46daea2006-11-03 19:33:44 -0600378 }
Dave Liuf5035922006-10-25 14:41:21 -0500379 } else if (max_data_rate >= 323) { /* it is DDR 333 */
380 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liua46daea2006-11-03 19:33:44 -0600381 /* DDR controller clk at 280~350 */
Dave Liuf5035922006-10-25 14:41:21 -0500382 effective_data_rate = 333; /* 6ns */
383 caslat = caslat;
384 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liua46daea2006-11-03 19:33:44 -0600385 /* DDR controller clk at 230~280 */
386 effective_data_rate = 266; /* 7.5ns */
Timur Tabiff0215a2006-11-28 12:09:35 -0600387 if (spd.clk_cycle2 == 0x75)
Dave Liuf5035922006-10-25 14:41:21 -0500388 caslat = caslat - 1;
Timur Tabiff0215a2006-11-28 12:09:35 -0600389 else
Dave Liua46daea2006-11-03 19:33:44 -0600390 caslat = caslat;
Dave Liuf5035922006-10-25 14:41:21 -0500391 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liua46daea2006-11-03 19:33:44 -0600392 /* DDR controller clk at 90~230 */
393 effective_data_rate = 200; /* 10ns */
Timur Tabiff0215a2006-11-28 12:09:35 -0600394 if (spd.clk_cycle3 == 0xa0)
Dave Liuf5035922006-10-25 14:41:21 -0500395 caslat = caslat - 2;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800396 else if (spd.clk_cycle2 == 0xa0)
Dave Liua46daea2006-11-03 19:33:44 -0600397 caslat = caslat - 1;
Timur Tabiff0215a2006-11-28 12:09:35 -0600398 else
Dave Liua46daea2006-11-03 19:33:44 -0600399 caslat = caslat;
Dave Liuf5035922006-10-25 14:41:21 -0500400 }
401 } else if (max_data_rate >= 256) { /* it is DDR 266 */
402 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liua46daea2006-11-03 19:33:44 -0600403 /* DDR controller clk at 280~350 */
Dave Liuf5035922006-10-25 14:41:21 -0500404 printf("DDR: DDR controller freq is more than "
405 "max data rate of the module\n");
406 return 0;
407 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liua46daea2006-11-03 19:33:44 -0600408 /* DDR controller clk at 230~280 */
Dave Liuf5035922006-10-25 14:41:21 -0500409 effective_data_rate = 266; /* 7.5ns */
410 caslat = caslat;
411 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liua46daea2006-11-03 19:33:44 -0600412 /* DDR controller clk at 90~230 */
413 effective_data_rate = 200; /* 10ns */
Timur Tabiff0215a2006-11-28 12:09:35 -0600414 if (spd.clk_cycle2 == 0xa0)
Dave Liuf5035922006-10-25 14:41:21 -0500415 caslat = caslat - 1;
Dave Liuf5035922006-10-25 14:41:21 -0500416 }
417 } else if (max_data_rate >= 190) { /* it is DDR 200 */
418 if (ddrc_clk <= 350 && ddrc_clk > 230) {
Dave Liua46daea2006-11-03 19:33:44 -0600419 /* DDR controller clk at 230~350 */
Dave Liuf5035922006-10-25 14:41:21 -0500420 printf("DDR: DDR controller freq is more than "
421 "max data rate of the module\n");
422 return 0;
423 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liua46daea2006-11-03 19:33:44 -0600424 /* DDR controller clk at 90~230 */
Dave Liuf5035922006-10-25 14:41:21 -0500425 effective_data_rate = 200; /* 10ns */
426 caslat = caslat;
427 }
Timur Tabiefec6302006-10-31 18:13:36 -0600428 }
429
Wolfgang Denkaf0501a2008-10-19 02:35:50 +0200430 debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
Dave Liua46daea2006-11-03 19:33:44 -0600431 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
Timur Tabiefec6302006-10-31 18:13:36 -0600432
Dave Liua46daea2006-11-03 19:33:44 -0600433 /*
434 * Errata DDR6 work around: input enable 2 cycles earlier.
Mario Six0344f5e2019-01-21 09:17:27 +0100435 * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
Dave Liua46daea2006-11-03 19:33:44 -0600436 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800437 if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
438 if (caslat == 2)
439 ddr->debug_reg = 0x201c0000; /* CL=2 */
440 else if (caslat == 3)
441 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
442 else if (caslat == 4)
443 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
Timur Tabiff0215a2006-11-28 12:09:35 -0600444
Mario Sixc463b6d2019-01-21 09:18:21 +0100445 sync();
Timur Tabiefec6302006-10-31 18:13:36 -0600446
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800447 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
448 }
Eran Liberty9095d4a2005-07-28 10:08:46 -0500449
450 /*
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800451 * Convert caslat clocks to DDR controller value.
452 * Force caslat_ctrl to be DDR Controller field-sized.
453 */
454 if (spd.mem_type == SPD_MEMTYPE_DDR) {
455 caslat_ctrl = (caslat + 1) & 0x07;
456 } else {
457 caslat_ctrl = (2 * caslat - 1) & 0x0f;
458 }
459
460 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
461 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
462 caslat, caslat_ctrl);
463
464 /*
465 * Timing Config 0.
466 * Avoid writing for DDR I.
467 */
468 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
469 unsigned char taxpd_clk = 8; /* By the book. */
470 unsigned char tmrd_clk = 2; /* By the book. */
471 unsigned char act_pd_exit = 2; /* Empirical? */
472 unsigned char pre_pd_exit = 6; /* Empirical? */
473
474 ddr->timing_cfg_0 = (0
475 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
476 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
477 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
478 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
479 );
480 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
481 }
482
483 /*
484 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
485 * use conservative value.
486 * For DDR II, they are bytes 36 and 37, in quarter nanos.
487 */
488
489 if (spd.mem_type == SPD_MEMTYPE_DDR) {
490 twr_clk = 3; /* Clocks */
491 twtr_clk = 1; /* Clocks */
492 } else {
493 twr_clk = picos_to_clk(spd.twr * 250);
494 twtr_clk = picos_to_clk(spd.twtr * 250);
Dave Liu6b051042009-02-25 12:31:32 +0800495 if (twtr_clk < 2)
496 twtr_clk = 2;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800497 }
498
499 /*
500 * Calculate Trfc, in picos.
501 * DDR I: Byte 42 straight up in ns.
502 * DDR II: Byte 40 and 42 swizzled some, in ns.
503 */
504 if (spd.mem_type == SPD_MEMTYPE_DDR) {
505 trfc = spd.trfc * 1000; /* up to ps */
506 } else {
507 unsigned int byte40_table_ps[8] = {
508 0,
509 250,
510 330,
511 500,
512 660,
513 750,
514 0,
515 0
516 };
517
518 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
519 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
520 }
521 trfc_clk = picos_to_clk(trfc);
522
523 /*
524 * Trcd, Byte 29, from quarter nanos to ps and clocks.
Eran Liberty9095d4a2005-07-28 10:08:46 -0500525 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800526 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
527
528 /*
529 * Convert trfc_clk to DDR controller fields. DDR I should
530 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
531 * 83xx controller has an extended REFREC field of three bits.
532 * The controller automatically adds 8 clocks to this value,
533 * so preadjust it down 8 first before splitting it up.
534 */
535 trfc_low = (trfc_clk - 8) & 0xf;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500536
537 ddr->timing_cfg_1 =
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800538 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
539 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
Wolfgang Denka1be4762008-05-20 16:00:29 +0200540 (trcd_clk << 20 ) | /* ACTTORW */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800541 (caslat_ctrl << 16 ) | /* CASLAT */
542 (trfc_low << 12 ) | /* REFEC */
543 ((twr_clk & 0x07) << 8) | /* WRRREC */
544 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
545 ((twtr_clk & 0x07) << 0) /* WRTORD */
546 );
547
548 /*
549 * Additive Latency
550 * For DDR I, 0.
551 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
552 * which comes from Trcd, and also note that:
553 * add_lat + caslat must be >= 4
554 */
555 add_lat = 0;
556 if (spd.mem_type == SPD_MEMTYPE_DDR2
557 && (odt_wr_cfg || odt_rd_cfg)
558 && (caslat < 4)) {
Dave Liu6b051042009-02-25 12:31:32 +0800559 add_lat = 4 - caslat;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800560 if ((add_lat + caslat) < 4) {
561 add_lat = 0;
562 }
563 }
564
565 /*
566 * Write Data Delay
567 * Historically 0x2 == 4/8 clock delay.
568 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
569 */
570 wr_data_delay = 2;
Andre Schwarz10ea0af2011-04-14 14:54:05 +0200571#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
572 wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
573#endif
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800574
575 /*
576 * Write Latency
577 * Read to Precharge
578 * Minimum CKE Pulse Width.
579 * Four Activate Window
580 */
581 if (spd.mem_type == SPD_MEMTYPE_DDR) {
582 /*
583 * This is a lie. It should really be 1, but if it is
584 * set to 1, bits overlap into the old controller's
585 * otherwise unused ACSM field. If we leave it 0, then
586 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
587 */
588 wr_lat = 0;
589
590 trtp_clk = 2; /* By the book. */
591 cke_min_clk = 1; /* By the book. */
592 four_act = 1; /* By the book. */
593
594 } else {
595 wr_lat = caslat - 1;
596
597 /* Convert SPD value from quarter nanos to picos. */
598 trtp_clk = picos_to_clk(spd.trtp * 250);
Dave Liu6b051042009-02-25 12:31:32 +0800599 if (trtp_clk < 2)
600 trtp_clk = 2;
601 trtp_clk += add_lat;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500602
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800603 cke_min_clk = 3; /* By the book. */
604 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
605 }
606
607 /*
608 * Empirically set ~MCAS-to-preamble override for DDR 2.
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500609 * Your mileage will vary.
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800610 */
611 cpo = 0;
612 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
Andre Schwarz10ea0af2011-04-14 14:54:05 +0200613#ifdef CONFIG_SYS_DDR_CPO
614 cpo = CONFIG_SYS_DDR_CPO;
615#else
Dave Liu939649a2008-01-10 23:09:33 +0800616 if (effective_data_rate == 266) {
617 cpo = 0x4; /* READ_LAT + 1/2 */
Dave Liu6b051042009-02-25 12:31:32 +0800618 } else if (effective_data_rate == 333) {
619 cpo = 0x6; /* READ_LAT + 1 */
620 } else if (effective_data_rate == 400) {
Dave Liub19ecd32007-09-18 12:37:57 +0800621 cpo = 0x7; /* READ_LAT + 5/4 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800622 } else {
623 /* Automatic calibration */
624 cpo = 0x1f;
625 }
Andre Schwarz10ea0af2011-04-14 14:54:05 +0200626#endif
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800627 }
628
629 ddr->timing_cfg_2 = (0
630 | ((add_lat & 0x7) << 28) /* ADD_LAT */
631 | ((cpo & 0x1f) << 23) /* CPO */
632 | ((wr_lat & 0x7) << 19) /* WR_LAT */
633 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
634 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
635 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
636 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
637 );
Eran Liberty9095d4a2005-07-28 10:08:46 -0500638
639 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
640 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
641
Dave Liuf5035922006-10-25 14:41:21 -0500642 /* Check DIMM data bus width */
Lee Nipper9f5d5762008-04-10 09:35:06 -0500643 if (spd.dataw_lsb < 64) {
Dave Liuc9fa31f2007-08-04 13:37:39 +0800644 if (spd.mem_type == SPD_MEMTYPE_DDR)
645 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
Dave Liu99e4d6c2007-08-10 15:48:59 +0800646 else
Dave Liuc9fa31f2007-08-04 13:37:39 +0800647 burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500648 debug("\n DDR DIMM: data bus width is 32 bit");
Dave Liua46daea2006-11-03 19:33:44 -0600649 } else {
Dave Liuf5035922006-10-25 14:41:21 -0500650 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500651 debug("\n DDR DIMM: data bus width is 64 bit");
Dave Liuf5035922006-10-25 14:41:21 -0500652 }
653
654 /* Is this an ECC DDR chip? */
Timur Tabiff0215a2006-11-28 12:09:35 -0600655 if (spd.config == 0x02)
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500656 debug(" with ECC\n");
Timur Tabiff0215a2006-11-28 12:09:35 -0600657 else
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500658 debug(" without ECC\n");
Dave Liuf5035922006-10-25 14:41:21 -0500659
660 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
661 Burst type is sequential
Eran Liberty9095d4a2005-07-28 10:08:46 -0500662 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800663 if (spd.mem_type == SPD_MEMTYPE_DDR) {
664 switch (caslat) {
Dave Liua46daea2006-11-03 19:33:44 -0600665 case 1:
666 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
667 break;
668 case 2:
669 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
670 break;
671 case 3:
672 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
673 break;
674 case 4:
675 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
676 break;
677 default:
678 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
679 return 0;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800680 }
681 } else {
682 mode_odt_enable = 0x0; /* Default disabled */
683 if (odt_wr_cfg || odt_rd_cfg) {
684 /*
685 * Bits 6 and 2 in Extended MRS(1)
686 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
687 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
688 */
689 mode_odt_enable = 0x40; /* 150 Ohm */
690 }
691
692 ddr->sdram_mode =
693 (0
694 | (1 << (16 + 10)) /* DQS Differential disable */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500695#ifdef CFG_SYS_DDR_MODE_WEAK
Andre Schwarz10ea0af2011-04-14 14:54:05 +0200696 | (1 << (16 + 1)) /* weak driver (~60%) */
697#endif
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800698 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
699 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
Xie Xiaobo53484322007-03-09 19:08:25 +0800700 | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800701 | (caslat << 4) /* caslat */
702 | (burstlen << 0) /* Burst length */
703 );
Eran Liberty9095d4a2005-07-28 10:08:46 -0500704 }
705 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
706
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800707 /*
708 * Clear EMRS2 and EMRS3.
709 */
710 ddr->sdram_mode2 = 0;
711 debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
712
Dave Liua46daea2006-11-03 19:33:44 -0600713 switch (spd.refresh) {
714 case 0x00:
715 case 0x80:
716 refresh_clk = picos_to_clk(15625000);
717 break;
718 case 0x01:
719 case 0x81:
720 refresh_clk = picos_to_clk(3900000);
721 break;
722 case 0x02:
723 case 0x82:
724 refresh_clk = picos_to_clk(7800000);
725 break;
726 case 0x03:
727 case 0x83:
728 refresh_clk = picos_to_clk(31300000);
729 break;
730 case 0x04:
731 case 0x84:
732 refresh_clk = picos_to_clk(62500000);
733 break;
734 case 0x05:
735 case 0x85:
736 refresh_clk = picos_to_clk(125000000);
737 break;
738 default:
739 refresh_clk = 0x512;
740 break;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500741 }
742
743 /*
744 * Set BSTOPRE to 0x100 for page mode
745 * If auto-charge is used, set BSTOPRE = 0
746 */
Dave Liua46daea2006-11-03 19:33:44 -0600747 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500748 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
749
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800750 /*
751 * SDRAM Cfg 2
752 */
753 odt_cfg = 0;
Dave Liub19ecd32007-09-18 12:37:57 +0800754#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800755 if (odt_rd_cfg | odt_wr_cfg) {
756 odt_cfg = 0x2; /* ODT to IOs during reads */
757 }
Dave Liub19ecd32007-09-18 12:37:57 +0800758#endif
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800759 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
760 ddr->sdram_cfg2 = (0
761 | (0 << 26) /* True DQS */
762 | (odt_cfg << 21) /* ODT only read */
763 | (1 << 12) /* 1 refresh at a time */
764 );
765
766 debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
767 }
768
Tom Rini6a5dccc2022-11-16 13:10:41 -0500769#ifdef CFG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
770 ddr->sdram_clk_cntl = CFG_SYS_DDR_SDRAM_CLK_CNTL;
Paul Gortmaker2bd9f1b2007-01-16 11:38:14 -0500771#endif
Dave Liuf5035922006-10-25 14:41:21 -0500772 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100773
Mario Sixc463b6d2019-01-21 09:18:21 +0100774 sync();
775 isync();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500776
Dave Liuf5035922006-10-25 14:41:21 -0500777 udelay(600);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500778
779 /*
Dave Liua46daea2006-11-03 19:33:44 -0600780 * Figure out the settings for the sdram_cfg register. Build up
781 * the value in 'sdram_cfg' before writing since the write into
Eran Liberty9095d4a2005-07-28 10:08:46 -0500782 * the register will actually enable the memory controller, and all
783 * settings must be done before enabling.
784 *
785 * sdram_cfg[0] = 1 (ddr sdram logic enable)
786 * sdram_cfg[1] = 1 (self-refresh-enable)
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800787 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
788 * 010 DDR 1 SDRAM
789 * 011 DDR 2 SDRAM
Dave Liuf5035922006-10-25 14:41:21 -0500790 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
791 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500792 */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800793 if (spd.mem_type == SPD_MEMTYPE_DDR)
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500794 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800795 else
Kim Phillips69257392007-08-17 09:30:00 -0500796 sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800797
798 sdram_cfg = (0
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500799 | SDRAM_CFG_MEM_EN /* DDR enable */
800 | SDRAM_CFG_SREN /* Self refresh */
801 | sdram_type /* SDRAM type */
Xie Xiaobo6149a5a2007-02-14 18:27:17 +0800802 );
Eran Liberty9095d4a2005-07-28 10:08:46 -0500803
Dave Liuf5035922006-10-25 14:41:21 -0500804 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
Timur Tabiff0215a2006-11-28 12:09:35 -0600805 if (spd.mod_attr & 0x02)
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500806 sdram_cfg |= SDRAM_CFG_RD_EN;
Dave Liuf5035922006-10-25 14:41:21 -0500807
808 /* The DIMM is 32bit width */
Lee Nipper9f5d5762008-04-10 09:35:06 -0500809 if (spd.dataw_lsb < 64) {
Dave Liuc9fa31f2007-08-04 13:37:39 +0800810 if (spd.mem_type == SPD_MEMTYPE_DDR)
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500811 sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
Dave Liuc9fa31f2007-08-04 13:37:39 +0800812 if (spd.mem_type == SPD_MEMTYPE_DDR2)
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500813 sdram_cfg |= SDRAM_CFG_32_BE;
Dave Liuc9fa31f2007-08-04 13:37:39 +0800814 }
Timur Tabiff0215a2006-11-28 12:09:35 -0600815
Dave Liuf5035922006-10-25 14:41:21 -0500816 ddrc_ecc_enable = 0;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500817
818#if defined(CONFIG_DDR_ECC)
Dave Liuf5035922006-10-25 14:41:21 -0500819 /* Enable ECC with sdram_cfg[2] */
Eran Liberty9095d4a2005-07-28 10:08:46 -0500820 if (spd.config == 0x02) {
Dave Liuf5035922006-10-25 14:41:21 -0500821 sdram_cfg |= 0x20000000;
822 ddrc_ecc_enable = 1;
823 /* disable error detection */
824 ddr->err_disable = ~ECC_ERROR_ENABLE;
825 /* set single bit error threshold to maximum value,
826 * reset counter to zero */
827 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
Dave Liua46daea2006-11-03 19:33:44 -0600828 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500829 }
Dave Liuf5035922006-10-25 14:41:21 -0500830
831 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
832 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500833#endif
Kim Phillips3b9c20f2007-08-16 22:52:48 -0500834 debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
Eran Liberty9095d4a2005-07-28 10:08:46 -0500835
Dave Liuf5035922006-10-25 14:41:21 -0500836 /* Enable controller, and GO! */
837 ddr->sdram_cfg = sdram_cfg;
Mario Sixc463b6d2019-01-21 09:18:21 +0100838 sync();
839 isync();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500840 udelay(500);
841
842 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
Rafal Jaworowski4a9b6aa2006-03-16 17:46:46 +0100843 return memsize; /*in MBytes*/
Eran Liberty9095d4a2005-07-28 10:08:46 -0500844}
Eran Liberty9095d4a2005-07-28 10:08:46 -0500845#endif /* CONFIG_SPD_EEPROM */
846
Peter Tysercb4731f2009-06-30 17:15:50 -0500847#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Mario Sixc463b6d2019-01-21 09:18:21 +0100848static inline u32 mftbu(void)
849{
850 u32 rval;
851
852 asm volatile("mftbu %0" : "=r" (rval));
853 return rval;
854}
855
856static inline u32 mftb(void)
857{
858 u32 rval;
859
860 asm volatile("mftb %0" : "=r" (rval));
861 return rval;
862}
863
Eran Liberty9095d4a2005-07-28 10:08:46 -0500864/*
Robert P. J. Daycbd618f2015-12-16 12:25:42 -0500865 * Use timebase counter, get_timer() is not available
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100866 * at this point of initialization yet.
Eran Liberty9095d4a2005-07-28 10:08:46 -0500867 */
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100868static __inline__ unsigned long get_tbms (void)
869{
870 unsigned long tbl;
871 unsigned long tbu1, tbu2;
872 unsigned long ms;
873 unsigned long long tmp;
874
875 ulong tbclk = get_tbclk();
876
877 /* get the timebase ticks */
878 do {
Mario Sixc463b6d2019-01-21 09:18:21 +0100879 tbu1 = mftbu();
880 tbl = mftb();
881 tbu2 = mftbu();
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100882 } while (tbu1 != tbu2);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500883
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100884 /* convert ticks to ms */
885 tmp = (unsigned long long)(tbu1);
886 tmp = (tmp << 32);
887 tmp += (unsigned long long)(tbl);
888 ms = tmp/(tbclk/1000);
889
890 return ms;
891}
892
893/*
894 * Initialize all of memory for ECC, then enable errors.
895 */
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100896void ddr_enable_ecc(unsigned int dram_size)
Eran Liberty9095d4a2005-07-28 10:08:46 -0500897{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200898 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Dave Liuf5035922006-10-25 14:41:21 -0500899 volatile ddr83xx_t *ddr= &immap->ddr;
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100900 unsigned long t_start, t_end;
Dave Liu8c84e472006-11-02 18:05:50 -0600901 register u64 *p;
902 register uint size;
903 unsigned int pattern[2];
Peter Tyser6f33a352009-06-30 17:15:51 -0500904
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100905 icache_enable();
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100906 t_start = get_tbms();
Dave Liu8c84e472006-11-02 18:05:50 -0600907 pattern[0] = 0xdeadbeef;
908 pattern[1] = 0xdeadbeef;
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100909
Dave Liu8c84e472006-11-02 18:05:50 -0600910 debug("ddr init: CPU FP write method\n");
911 size = dram_size;
912 for (p = 0; p < (u64*)(size); p++) {
913 ppcDWstore((u32*)p, pattern);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500914 }
Mario Sixc463b6d2019-01-21 09:18:21 +0100915 sync();
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100916
917 t_end = get_tbms();
918 icache_disable();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500919
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100920 debug("\nREADY!!\n");
921 debug("ddr init duration: %ld ms\n", t_end - t_start);
922
923 /* Clear All ECC Errors */
924 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
925 ddr->err_detect |= ECC_ERROR_DETECT_MME;
926 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
927 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
928 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
929 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
930 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
931 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
932
933 /* Disable ECC-Interrupts */
934 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
935
936 /* Enable errors for ECC */
937 ddr->err_disable &= ECC_ERROR_ENABLE;
938
Mario Sixc463b6d2019-01-21 09:18:21 +0100939 sync();
940 isync();
Marian Balakowicz6f6104d2006-03-14 16:23:35 +0100941}
Eran Liberty9095d4a2005-07-28 10:08:46 -0500942#endif /* CONFIG_DDR_ECC */
Mario Six538b5752018-08-06 10:23:30 +0200943
944#endif /* !CONFIG_MPC83XX_SDRAM */