Tom Rini | cb896f5 | 2018-07-13 09:05:05 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 2 | /* |
Tien Fong Chee | b26072a | 2021-11-07 23:08:54 +0800 | [diff] [blame] | 3 | * Copyright (C) 2012-2021 Altera Corporation <www.altera.com> |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame^] | 6 | #include <config.h> |
Simon Glass | 1d91ba7 | 2019-11-14 12:57:37 -0700 | [diff] [blame] | 7 | #include <cpu_func.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 8 | #include <hang.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/pl310.h> |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 13 | #include <asm/utils.h> |
| 14 | #include <image.h> |
| 15 | #include <asm/arch/reset_manager.h> |
| 16 | #include <spl.h> |
| 17 | #include <asm/arch/system_manager.h> |
| 18 | #include <asm/arch/freeze_controller.h> |
| 19 | #include <asm/arch/clock_manager.h> |
| 20 | #include <asm/arch/scan_manager.h> |
| 21 | #include <asm/arch/sdram.h> |
| 22 | #include <asm/arch/scu.h> |
Marek Vasut | 95db8ee | 2018-07-30 13:58:54 +0200 | [diff] [blame] | 23 | #include <asm/arch/misc.h> |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 24 | #include <asm/arch/nic301.h> |
| 25 | #include <asm/sections.h> |
| 26 | #include <fdtdec.h> |
| 27 | #include <watchdog.h> |
| 28 | #include <asm/arch/pinmux.h> |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 29 | #include <asm/arch/fpga_manager.h> |
| 30 | #include <mmc.h> |
| 31 | #include <memalign.h> |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 32 | #include <linux/delay.h> |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 33 | |
| 34 | #define FPGA_BUFSIZ 16 * 1024 |
Tien Fong Chee | b26072a | 2021-11-07 23:08:54 +0800 | [diff] [blame] | 35 | #define FSBL_IMAGE_IS_VALID 0x49535756 |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 36 | |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 37 | #define FSBL_IMAGE_IS_INVALID 0x0 |
| 38 | #define BOOTROM_CONFIGURES_IO_PINMUX 0x3 |
| 39 | |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 40 | DECLARE_GLOBAL_DATA_PTR; |
| 41 | |
Ley Foon Tan | f7fcc90 | 2020-03-06 16:55:20 +0800 | [diff] [blame] | 42 | #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 43 | #define BOOTROM_SHARED_MEM_ADDR (CFG_SYS_INIT_RAM_ADDR + \ |
Ley Foon Tan | f7fcc90 | 2020-03-06 16:55:20 +0800 | [diff] [blame] | 44 | SOCFPGA_PHYS_OCRAM_SIZE - \ |
| 45 | BOOTROM_SHARED_MEM_SIZE) |
| 46 | #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438) |
Marek Behún | 4bebdd3 | 2021-05-20 13:23:52 +0200 | [diff] [blame] | 47 | static u32 rst_mgr_status __section(".data"); |
Ley Foon Tan | f7fcc90 | 2020-03-06 16:55:20 +0800 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Bootrom will clear the status register in reset manager and stores the |
| 51 | * reset status value in shared memory. Bootrom stores shared data at last |
| 52 | * 2KB of onchip RAM. |
| 53 | * This function save reset status provided by BootROM to rst_mgr_status. |
| 54 | * More information about reset status register value can be found in reset |
| 55 | * manager register description. |
| 56 | * When running in debugger without Bootrom, r0 to r3 are random values. |
| 57 | * So, skip save the value when r0 is not BootROM shared data address. |
| 58 | * |
| 59 | * r0 - Contains the pointer to the shared memory block. The shared |
| 60 | * memory block is located in the top 2 KB of on-chip RAM. |
| 61 | * r1 - contains the length of the shared memory. |
| 62 | * r2 - unused and set to 0x0. |
| 63 | * r3 - points to the version block. |
| 64 | */ |
| 65 | void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, |
| 66 | unsigned long r3) |
| 67 | { |
| 68 | if (r0 == BOOTROM_SHARED_MEM_ADDR) |
| 69 | rst_mgr_status = readl(RST_STATUS_SHARED_ADDR); |
| 70 | |
| 71 | save_boot_params_ret(); |
| 72 | } |
| 73 | |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 74 | u32 spl_boot_device(void) |
| 75 | { |
Ley Foon Tan | 3d3a860 | 2019-11-08 10:38:20 +0800 | [diff] [blame] | 76 | const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 77 | |
| 78 | switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) { |
| 79 | case 0x1: /* FPGA (HPS2FPGA Bridge) */ |
| 80 | return BOOT_DEVICE_RAM; |
| 81 | case 0x2: /* NAND Flash (1.8V) */ |
| 82 | case 0x3: /* NAND Flash (3.0V) */ |
| 83 | socfpga_per_reset(SOCFPGA_RESET(NAND), 0); |
| 84 | return BOOT_DEVICE_NAND; |
| 85 | case 0x4: /* SD/MMC External Transceiver (1.8V) */ |
| 86 | case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ |
| 87 | socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0); |
| 88 | socfpga_per_reset(SOCFPGA_RESET(DMA), 0); |
| 89 | return BOOT_DEVICE_MMC1; |
| 90 | case 0x6: /* QSPI Flash (1.8V) */ |
| 91 | case 0x7: /* QSPI Flash (3.0V) */ |
| 92 | socfpga_per_reset(SOCFPGA_RESET(QSPI), 0); |
| 93 | return BOOT_DEVICE_SPI; |
| 94 | default: |
| 95 | printf("Invalid boot device (bsel=%08x)!\n", bsel); |
| 96 | hang(); |
| 97 | } |
| 98 | } |
| 99 | |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 100 | #ifdef CONFIG_SPL_MMC |
Andre Przywara | 3cb12ef | 2021-07-12 11:06:49 +0100 | [diff] [blame] | 101 | u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 102 | { |
Tien Fong Chee | 6091dd1 | 2019-01-23 14:20:05 +0800 | [diff] [blame] | 103 | #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 104 | return MMCSD_MODE_FS; |
| 105 | #else |
| 106 | return MMCSD_MODE_RAW; |
| 107 | #endif |
| 108 | } |
| 109 | #endif |
| 110 | |
| 111 | void spl_board_init(void) |
| 112 | { |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 113 | int ret; |
| 114 | |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 115 | ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ); |
| 116 | |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 117 | /* enable console uart printing */ |
| 118 | preloader_console_init(); |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 119 | schedule(); |
Marek Vasut | 95db8ee | 2018-07-30 13:58:54 +0200 | [diff] [blame] | 120 | |
Marek Vasut | 8fdb419 | 2018-08-18 19:11:52 +0200 | [diff] [blame] | 121 | arch_early_init_r(); |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 122 | |
| 123 | /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */ |
Michał Barnaś | 8fdccae | 2024-03-19 18:18:13 +0000 | [diff] [blame] | 124 | if ((IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && |
| 125 | is_regular_boot_valid()) || |
| 126 | (!IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) && |
| 127 | is_fpgamgr_user_mode())) { |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 128 | ret = config_pins(gd->fdt_blob, "shared"); |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 129 | if (ret) |
| 130 | return; |
| 131 | |
| 132 | ret = config_pins(gd->fdt_blob, "fpga"); |
| 133 | if (ret) |
| 134 | return; |
Michał Barnaś | 8fdccae | 2024-03-19 18:18:13 +0000 | [diff] [blame] | 135 | } else if (IS_ENABLED(CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM) || |
| 136 | !is_fpgamgr_early_user_mode()) { |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 137 | /* Program IOSSM(early IO release) or full FPGA */ |
| 138 | fpgamgr_program(buf, FPGA_BUFSIZ, 0); |
Tien Fong Chee | adc079f | 2021-11-07 23:08:56 +0800 | [diff] [blame] | 139 | |
| 140 | /* Skipping double program for combined RBF */ |
| 141 | if (!is_fpgamgr_user_mode()) { |
| 142 | /* |
| 143 | * Expect FPGA entered early user mode, so |
| 144 | * the flag is set to re-program IOSSM |
| 145 | */ |
| 146 | force_periph_program(true); |
| 147 | |
| 148 | /* Re-program IOSSM to stabilize IO system */ |
| 149 | fpgamgr_program(buf, FPGA_BUFSIZ, 0); |
| 150 | |
| 151 | force_periph_program(false); |
| 152 | } |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | /* If the IOSSM/full FPGA is already loaded, start DDR */ |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 156 | if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode()) { |
| 157 | if (!is_regular_boot_valid()) { |
| 158 | /* |
| 159 | * Ensure all signals in stable state before triggering |
| 160 | * warm reset. This value is recommended from stress |
| 161 | * test. |
| 162 | */ |
| 163 | mdelay(10); |
| 164 | |
| 165 | #if IS_ENABLED(CONFIG_CADENCE_QSPI) |
| 166 | /* |
| 167 | * Trigger software reset to QSPI flash. |
| 168 | * On some boards, the QSPI flash reset may not be |
| 169 | * connected to the HPS warm reset. |
| 170 | */ |
| 171 | qspi_flash_software_reset(); |
| 172 | #endif |
| 173 | |
| 174 | ret = readl(socfpga_get_rstmgr_addr() + |
| 175 | RSTMGR_A10_SYSWARMMASK); |
| 176 | /* |
| 177 | * Masking s2f & FPGA manager module reset from warm |
| 178 | * reset |
| 179 | */ |
| 180 | writel(ret & (~(ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK | |
| 181 | ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK)), |
| 182 | socfpga_get_rstmgr_addr() + |
| 183 | RSTMGR_A10_SYSWARMMASK); |
| 184 | |
| 185 | /* |
| 186 | * BootROM will configure both IO and pin mux after a |
| 187 | * warm reset |
| 188 | */ |
| 189 | ret = readl(socfpga_get_sysmgr_addr() + |
| 190 | SYSMGR_A10_ROMCODE_CTRL); |
| 191 | writel(ret | BOOTROM_CONFIGURES_IO_PINMUX, |
| 192 | socfpga_get_sysmgr_addr() + |
| 193 | SYSMGR_A10_ROMCODE_CTRL); |
| 194 | |
| 195 | /* |
| 196 | * Up to here, image is considered valid and should be |
| 197 | * set as valid before warm reset is triggered |
| 198 | */ |
| 199 | writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + |
| 200 | SYSMGR_A10_ROMCODE_INITSWSTATE); |
| 201 | |
| 202 | /* |
| 203 | * Set this flag to scratch register, so that a proper |
| 204 | * boot progress before / after warm reset can be |
| 205 | * tracked by FSBL |
| 206 | */ |
| 207 | set_regular_boot(true); |
| 208 | |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 209 | schedule(); |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 210 | |
| 211 | reset_cpu(); |
| 212 | } |
| 213 | |
| 214 | /* |
| 215 | * Reset this flag to scratch register, so that a proper |
| 216 | * boot progress before / after warm reset can be |
| 217 | * tracked by FSBL |
| 218 | */ |
| 219 | set_regular_boot(false); |
| 220 | |
| 221 | ret = readl(socfpga_get_rstmgr_addr() + |
| 222 | RSTMGR_A10_SYSWARMMASK); |
| 223 | |
| 224 | /* |
| 225 | * Unmasking s2f & FPGA manager module reset from warm |
| 226 | * reset |
| 227 | */ |
| 228 | writel(ret | ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK | |
| 229 | ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK, |
| 230 | socfpga_get_rstmgr_addr() + RSTMGR_A10_SYSWARMMASK); |
| 231 | |
| 232 | /* |
| 233 | * Up to here, MPFE hang workaround is considered done and |
| 234 | * should be reset as invalid until FSBL successfully loading |
| 235 | * SSBL, and prepare jumping to SSBL, then only setting as |
| 236 | * valid |
| 237 | */ |
| 238 | writel(FSBL_IMAGE_IS_INVALID, socfpga_get_sysmgr_addr() + |
| 239 | SYSMGR_A10_ROMCODE_INITSWSTATE); |
| 240 | |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 241 | ddr_calibration_sequence(); |
Tien Fong Chee | 8ca1708 | 2021-11-07 23:08:55 +0800 | [diff] [blame] | 242 | } |
Tien Fong Chee | fe03d80 | 2019-05-07 17:42:30 +0800 | [diff] [blame] | 243 | |
| 244 | if (!is_fpgamgr_user_mode()) |
| 245 | fpgamgr_program(buf, FPGA_BUFSIZ, 0); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 246 | } |
| 247 | |
| 248 | void board_init_f(ulong dummy) |
| 249 | { |
Ley Foon Tan | fed4c95 | 2019-11-08 10:38:19 +0800 | [diff] [blame] | 250 | if (spl_early_init()) |
| 251 | hang(); |
| 252 | |
| 253 | socfpga_get_managers_addr(); |
| 254 | |
Marek Vasut | 339da98 | 2018-05-08 20:32:01 +0200 | [diff] [blame] | 255 | dcache_disable(); |
| 256 | |
Marek Vasut | 8fdb419 | 2018-08-18 19:11:52 +0200 | [diff] [blame] | 257 | socfpga_init_security_policies(); |
| 258 | socfpga_sdram_remap_zero(); |
Marek Vasut | a62817a | 2019-03-09 22:25:57 +0100 | [diff] [blame] | 259 | socfpga_pl310_clear(); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 260 | |
Marek Vasut | 8fdb419 | 2018-08-18 19:11:52 +0200 | [diff] [blame] | 261 | /* Assert reset to all except L4WD0 and L4TIMER0 */ |
| 262 | socfpga_per_reset_all(); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 263 | socfpga_watchdog_disable(); |
| 264 | |
Marek Vasut | 8fdb419 | 2018-08-18 19:11:52 +0200 | [diff] [blame] | 265 | /* Configure the clock based on handoff */ |
| 266 | cm_basic_init(gd->fdt_blob); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 267 | |
| 268 | #ifdef CONFIG_HW_WATCHDOG |
| 269 | /* release osc1 watchdog timer 0 from reset */ |
| 270 | socfpga_reset_deassert_osc1wd0(); |
| 271 | |
| 272 | /* reconfigure and enable the watchdog */ |
| 273 | hw_watchdog_init(); |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 274 | schedule(); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 275 | #endif /* CONFIG_HW_WATCHDOG */ |
Marek Vasut | 8fdb419 | 2018-08-18 19:11:52 +0200 | [diff] [blame] | 276 | |
| 277 | config_dedicated_pins(gd->fdt_blob); |
Stefan Roese | 80877fa | 2022-09-02 14:10:46 +0200 | [diff] [blame] | 278 | schedule(); |
Ley Foon Tan | 3305ba7 | 2018-05-24 00:17:27 +0800 | [diff] [blame] | 279 | } |
Tien Fong Chee | b26072a | 2021-11-07 23:08:54 +0800 | [diff] [blame] | 280 | |
| 281 | /* board specific function prior loading SSBL / U-Boot proper */ |
| 282 | void spl_board_prepare_for_boot(void) |
| 283 | { |
| 284 | writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + |
| 285 | SYSMGR_A10_ROMCODE_INITSWSTATE); |
| 286 | } |