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git01.mediatek.com / filogic / uboot / de66a4135983f8222a09dfa77852de9ab849fcc5 / . / arch / arm / dts / socfpga_stratix10_socdk.dts
blob: 2745050810ff4509e72b1b2aed941a71bc6d3862 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]2/*
3 * Copyright (C) 2018 Intel Corporation
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]4 */
5
6#include "socfpga_stratix10.dtsi"
7
8/ {
9 model = "SoCFPGA Stratix 10 SoCDK";
10
11 aliases {
12 serial0 = &uart0;
13 };
14
15 chosen {
16 stdout-path = "serial0:115200n8";
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 hps0 {
22 label = "hps_led0";
23 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
24 };
25
26 hps1 {
27 label = "hps_led1";
28 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
29 };
30
31 hps2 {
32 label = "hps_led2";
33 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
34 };
35 };
36
37 memory {
38 device_type = "memory";
Ley Foon Tanb9ff1532019-03-22 01:24:03 +0800[diff] [blame]39 /* 4GB */
40 reg = <0 0x00000000 0 0x80000000>,
41 <1 0x80000000 0 0x80000000>;
Ley Foon Tanad259df2018-07-12 19:13:33 +0800[diff] [blame]42 u-boot,dm-pre-reloc;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]43 };
44};
45
46&gpio1 {
47 status = "okay";
48};
49
50&gmac0 {
51 status = "okay";
52 phy-mode = "rgmii";
53 phy-handle = <&phy0>;
54
55 max-frame-size = <3800>;
56
57 mdio0 {
58 #address-cells = <1>;
59 #size-cells = <0>;
60 compatible = "snps,dwmac-mdio";
61 phy0: ethernet-phy@0 {
62 reg = <4>;
63
64 txd0-skew-ps = <0>; /* -420ps */
65 txd1-skew-ps = <0>; /* -420ps */
66 txd2-skew-ps = <0>; /* -420ps */
67 txd3-skew-ps = <0>; /* -420ps */
68 rxd0-skew-ps = <420>; /* 0ps */
69 rxd1-skew-ps = <420>; /* 0ps */
70 rxd2-skew-ps = <420>; /* 0ps */
71 rxd3-skew-ps = <420>; /* 0ps */
72 txen-skew-ps = <0>; /* -420ps */
73 txc-skew-ps = <1860>; /* 960ps */
74 rxdv-skew-ps = <420>; /* 0ps */
75 rxc-skew-ps = <1680>; /* 780ps */
76 };
77 };
78};
79
80&mmc {
81 status = "okay";
82 cap-sd-highspeed;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +0800[diff] [blame]83 cap-mmc-highspeed;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]84 broken-cd;
85 bus-width = <4>;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +0800[diff] [blame]86 drvsel = <3>;
87 smplsel = <0>;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]88};
89
Ley Foon Tan2f59cf12019-04-03 13:45:02 +0800[diff] [blame]90&qspi {
91 flash0: flash@0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "n25q00a";
95 reg = <0>;
96 spi-max-frequency = <50000000>;
97
98 m25p,fast-read;
99 cdns,page-size = <256>;
100 cdns,block-size = <16>;
101 cdns,read-delay = <1>;
102 cdns,tshsl-ns = <50>;
103 cdns,tsd2d-ns = <50>;
104 cdns,tchsh-ns = <4>;
105 cdns,tslch-ns = <4>;
106
107 partitions {
108 compatible = "fixed-partitions";
109 #address-cells = <1>;
110 #size-cells = <1>;
111
112 qspi_boot: partition@0 {
113 label = "Boot and fpga data";
114 reg = <0x0 0x4000000>;
115 };
116
117 qspi_rootfs: partition@4000000 {
118 label = "Root Filesystem - JFFS2";
119 reg = <0x4000000 0x4000000>;
120 };
121 };
122 };
123};
124
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -0600[diff] [blame]125&uart0 {
126 status = "okay";
127};
128
129&usb0 {
130 status = "okay";
131};