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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -06002/*
3 * Copyright (C) 2018 Intel Corporation
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -06004 */
5
6#include "socfpga_stratix10.dtsi"
7
8/ {
9 model = "SoCFPGA Stratix 10 SoCDK";
10
11 aliases {
12 serial0 = &uart0;
13 };
14
15 chosen {
16 stdout-path = "serial0:115200n8";
17 };
18
19 leds {
20 compatible = "gpio-leds";
21 hps0 {
22 label = "hps_led0";
23 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
24 };
25
26 hps1 {
27 label = "hps_led1";
28 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
29 };
30
31 hps2 {
32 label = "hps_led2";
33 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 /* We expect the bootloader to fill in the reg */
40 reg = <0 0 0 0>;
41 };
42};
43
44&gpio1 {
45 status = "okay";
46};
47
48&gmac0 {
49 status = "okay";
50 phy-mode = "rgmii";
51 phy-handle = <&phy0>;
52
53 max-frame-size = <3800>;
54
55 mdio0 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 compatible = "snps,dwmac-mdio";
59 phy0: ethernet-phy@0 {
60 reg = <4>;
61
62 txd0-skew-ps = <0>; /* -420ps */
63 txd1-skew-ps = <0>; /* -420ps */
64 txd2-skew-ps = <0>; /* -420ps */
65 txd3-skew-ps = <0>; /* -420ps */
66 rxd0-skew-ps = <420>; /* 0ps */
67 rxd1-skew-ps = <420>; /* 0ps */
68 rxd2-skew-ps = <420>; /* 0ps */
69 rxd3-skew-ps = <420>; /* 0ps */
70 txen-skew-ps = <0>; /* -420ps */
71 txc-skew-ps = <1860>; /* 960ps */
72 rxdv-skew-ps = <420>; /* 0ps */
73 rxc-skew-ps = <1680>; /* 780ps */
74 };
75 };
76};
77
78&mmc {
79 status = "okay";
80 cap-sd-highspeed;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +080081 cap-mmc-highspeed;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -060082 broken-cd;
83 bus-width = <4>;
Ley Foon Tan80a77ad2018-05-18 22:05:35 +080084 drvsel = <3>;
85 smplsel = <0>;
Dinh Nguyen41ca4ca2018-03-08 21:39:26 -060086};
87
88&uart0 {
89 status = "okay";
90};
91
92&usb0 {
93 status = "okay";
94};