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git01.mediatek.com / filogic / uboot / de649e64b4f6f56bfb8ae91190e7a43aa6792443 / . / arch / arm / dts / k3-am65.dtsi
blob: 3d89bf32a9d14356c1abd1d7503cb5c55e3ac607 [file] [log] [blame]
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
Andreas Dannenbergd20cf7b2019-06-04 18:08:15 -0500[diff] [blame]11#include <dt-bindings/pinctrl/k3.h>
Lokesh Vutla61ff6a32019-06-07 19:24:47 +0530[diff] [blame]12#include <dt-bindings/soc/ti,sci_pm_domain.h>
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]13
14/ {
15 model = "Texas Instruments K3 AM654 SoC";
16 compatible = "ti,am654";
17 interrupt-parent = <&gic500>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]21 aliases {
22 serial0 = &wkup_uart0;
23 serial1 = &mcu_uart0;
24 serial2 = &main_uart0;
25 serial3 = &main_uart1;
26 serial4 = &main_uart2;
Andreas Dannenberge3179be2019-06-04 18:08:14 -0500[diff] [blame]27 i2c0 = &wkup_i2c0;
28 i2c1 = &mcu_i2c0;
29 i2c2 = &main_i2c0;
30 i2c3 = &main_i2c1;
31 i2c4 = &main_i2c2;
32 i2c5 = &main_i2c3;
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]33 spi0 = &ospi0;
34 spi1 = &ospi1;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]35 };
36
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]37 chosen { };
38
39 firmware {
40 optee {
41 compatible = "linaro,optee-tz";
42 method = "smc";
43 };
44
45 psci: psci {
46 compatible = "arm,psci-1.0";
47 method = "smc";
48 };
49 };
50
51 a53_timer0: timer-cl0-cpu0 {
52 compatible = "arm,armv8-timer";
53 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
54 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
55 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
56 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
57 };
58
59 pmu: pmu {
60 compatible = "arm,armv8-pmuv3";
61 /* Recommendation from GIC500 TRM Table A.3 */
62 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
63 };
64
65 cbass_main: interconnect@100000 {
66 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]67 #address-cells = <2>;
68 #size-cells = <2>;
69 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
70 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
71 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
72 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
73 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
Sekhar Nori956760a2019-08-01 19:13:00 +0530[diff] [blame]74 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]75 /* MCUSS Range */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]76 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
77 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]78 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
Suman Anna2604d8d2019-10-17 09:03:08 +0530[diff] [blame]79 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
80 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]81 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
82 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
83 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]84 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
85 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
86 <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
87 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
88 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]89
90 cbass_mcu: interconnect@28380000 {
91 compatible = "simple-bus";
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]92 #address-cells = <2>;
93 #size-cells = <2>;
94 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
95 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]96 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
Suman Anna2604d8d2019-10-17 09:03:08 +0530[diff] [blame]97 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
98 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]99 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
100 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
101 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]102 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
103 <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */
104 <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
105 <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]106
107 cbass_wakeup: interconnect@42040000 {
108 compatible = "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 /* WKUP Basic peripherals */
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]112 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
Lokesh Vutla8bfaf012018-08-27 15:59:08 +0530[diff] [blame]113 };
114 };
115 };
116};
117
118/* Now include the peripherals for each bus segments */
119#include "k3-am65-main.dtsi"
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]120#include "k3-am65-mcu.dtsi"
121#include "k3-am65-wakeup.dtsi"