Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 1 | /* |
Bin Meng | 7557405 | 2016-02-05 19:30:11 -0800 | [diff] [blame] | 2 | * U-Boot - Configuration file for BF533 EZKIT board |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 3 | */ |
| 4 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 5 | #ifndef __CONFIG_BF533_EZKIT_H__ |
| 6 | #define __CONFIG_BF533_EZKIT_H__ |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 7 | |
Mike Frysinger | 18a407c | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 8 | #include <asm/config-pre.h> |
Mike Frysinger | f0dd792 | 2008-02-18 05:26:48 -0500 | [diff] [blame] | 9 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 10 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 11 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 12 | * Processor Settings |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 13 | */ |
Mike Frysinger | 5b0c128 | 2010-12-23 14:58:37 -0500 | [diff] [blame] | 14 | #define CONFIG_BFIN_CPU bf533-0.3 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
Jon Loeliger | 5c4ddae | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 16 | |
| 17 | |
| 18 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 22 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 27000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
| 33 | #define CONFIG_VCO_MULT 22 |
| 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 36 | #define CONFIG_CCLK_DIV 1 |
| 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
| 39 | #define CONFIG_SCLK_DIV 5 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 40 | |
Jon Loeliger | 8262ada | 2007-07-04 22:31:49 -0500 | [diff] [blame] | 41 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 42 | /* |
| 43 | * Memory Settings |
| 44 | */ |
| 45 | #define CONFIG_MEM_SIZE 32 |
| 46 | /* Early EZKITs had 32megs, but later have 64megs */ |
| 47 | #if (CONFIG_MEM_SIZE == 64) |
| 48 | # define CONFIG_MEM_ADD_WDTH 10 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 49 | #else |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 50 | # define CONFIG_MEM_ADD_WDTH 9 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 51 | #endif |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 52 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 53 | #define CONFIG_EBIU_SDRRC_VAL 0x398 |
| 54 | #define CONFIG_EBIU_SDGCTL_VAL 0x91118d |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 55 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 56 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
| 57 | #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 |
| 58 | #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 59 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 60 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
| 61 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 62 | |
| 63 | |
| 64 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 65 | * Network Settings |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 66 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 67 | #define ADI_CMDS_NETWORK 1 |
Ben Warren | 0fd6aae | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 68 | #define CONFIG_SMC91111 1 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 69 | #define CONFIG_SMC91111_BASE 0x20310300 |
| 70 | #define SMC91111_EEPROM_INIT() \ |
| 71 | do { \ |
Ben Warren | 0fd6aae | 2009-10-04 22:37:03 -0700 | [diff] [blame] | 72 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
| 73 | bfin_write_FIO_FLAG_C(PF1); \ |
| 74 | bfin_write_FIO_FLAG_S(PF0); \ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 75 | SSYNC(); \ |
| 76 | } while (0) |
| 77 | #define CONFIG_HOSTNAME bf533-ezkit |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 78 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 79 | |
| 80 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 81 | * Flash Settings |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 82 | */ |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 83 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 84 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 |
| 85 | #define CONFIG_SYS_MAX_FLASH_SECT 40 |
| 86 | #define CONFIG_ENV_IS_IN_FLASH |
Mike Frysinger | ce6b6c8 | 2009-09-21 18:04:49 -0400 | [diff] [blame] | 87 | #define CONFIG_ENV_ADDR 0x20030000 |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 88 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 89 | #define FLASH_TOT_SECT 40 |
| 90 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 91 | |
| 92 | /* |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 93 | * I2C Settings |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 94 | */ |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 95 | #define CONFIG_SYS_I2C_SOFT |
| 96 | #ifdef CONFIG_SYS_I2C_SOFT |
| 97 | #define CONFIG_SYS_I2C |
Mike Frysinger | d86e9a7 | 2010-06-08 16:22:44 -0400 | [diff] [blame] | 98 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0 |
| 99 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1 |
Heiko Schocher | 479a4cf | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 100 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 |
| 101 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 |
| 102 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 103 | #endif |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 104 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 105 | /* |
| 106 | * Misc Settings |
| 107 | */ |
| 108 | #define CONFIG_MISC_INIT_R |
| 109 | #define CONFIG_RTC_BFIN |
| 110 | #define CONFIG_UART_CONSOLE 0 |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 111 | |
Mike Frysinger | 62d2a23 | 2008-06-01 09:09:48 -0400 | [diff] [blame] | 112 | /* |
| 113 | * Pull in common ADI header for remaining command/environment setup |
| 114 | */ |
| 115 | #include <configs/bfin_adi_common.h> |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 116 | |
Aubrey.Li | 9da597f | 2007-03-09 13:38:44 +0800 | [diff] [blame] | 117 | #endif |