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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babic1c2b3ac2011-01-20 07:49:52 +00002/*
3 * (C) Copyright 2011
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
Stefano Babic1c2b3ac2011-01-20 07:49:52 +00005 */
6
7#ifndef __ASM_ARCH_CLOCK_H
8#define __ASM_ARCH_CLOCK_H
9
Benoît Thébaudeaue4528342012-08-21 11:07:20 +000010#ifdef CONFIG_MX35_HCLK_FREQ
11#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
12#else
13#define MXC_HCLK 24000000
14#endif
15
16#ifdef CONFIG_MX35_CLK32
17#define MXC_CLK32 CONFIG_MX35_CLK32
18#else
19#define MXC_CLK32 32768
20#endif
21
Stefano Babic1c2b3ac2011-01-20 07:49:52 +000022enum mxc_clock {
Benoît Thébaudeauefc91872012-08-14 10:32:21 +000023 MXC_ARM_CLK,
Stefano Babic1c2b3ac2011-01-20 07:49:52 +000024 MXC_AHB_CLK,
25 MXC_IPG_CLK,
26 MXC_IPG_PERCLK,
27 MXC_UART_CLK,
Benoît Thébaudeau8eae5692012-09-27 10:26:02 +000028 MXC_ESDHC1_CLK,
29 MXC_ESDHC2_CLK,
30 MXC_ESDHC3_CLK,
Stefano Babic1c2b3ac2011-01-20 07:49:52 +000031 MXC_USB_CLK,
32 MXC_CSPI_CLK,
33 MXC_FEC_CLK,
Matthias Weisser99ba3422012-09-24 02:46:53 +000034 MXC_I2C_CLK,
Stefano Babic1c2b3ac2011-01-20 07:49:52 +000035};
36
Benoît Thébaudeauefc91872012-08-14 10:32:21 +000037enum mxc_main_clock {
38 CPU_CLK,
39 AHB_CLK,
40 IPG_CLK,
41 IPG_PER_CLK,
42 NFC_CLK,
43 USB_CLK,
44 HSP_CLK,
45};
46
47enum mxc_peri_clock {
48 UART1_BAUD,
49 UART2_BAUD,
50 UART3_BAUD,
51 SSI1_BAUD,
52 SSI2_BAUD,
53 CSI_BAUD,
54 MSHC_CLK,
55 ESDHC1_CLK,
56 ESDHC2_CLK,
57 ESDHC3_CLK,
58 SPDIF_CLK,
59 SPI1_CLK,
60 SPI2_CLK,
61};
62
Stefano Babic1c2b3ac2011-01-20 07:49:52 +000063u32 imx_get_uartclk(void);
64u32 imx_get_fecclk(void);
65unsigned int mxc_get_clock(enum mxc_clock clk);
66
67#endif /* __ASM_ARCH_CLOCK_H */