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Thomas Chou3a673f12010-04-30 11:34:16 +08001/*
2 * Altera SPI driver
3 *
4 * based on bfin_spi.c
5 * Copyright (c) 2005-2008 Analog Devices Inc.
6 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
7 *
Jagannadha Sutradharudu Tekid92799e2013-10-14 13:31:24 +05308 * SPDX-License-Identifier: GPL-2.0+
Thomas Chou3a673f12010-04-30 11:34:16 +08009 */
10#include <common.h>
Thomas Chouc5899542015-10-14 08:33:34 +080011#include <dm.h>
12#include <errno.h>
Thomas Chou3a673f12010-04-30 11:34:16 +080013#include <malloc.h>
Thomas Chouc5899542015-10-14 08:33:34 +080014#include <fdtdec.h>
Jagan Tekia6f48752015-10-27 23:11:11 +053015#include <spi.h>
Thomas Chouc5899542015-10-14 08:33:34 +080016#include <asm/io.h>
17
18DECLARE_GLOBAL_DATA_PTR;
Thomas Chou3a673f12010-04-30 11:34:16 +080019
Jagan Tekia6f48752015-10-27 23:11:11 +053020#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
21#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
22
Marek Vasut7bb4fc32014-10-22 21:56:04 +020023#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
Jagan Tekia6f48752015-10-27 23:11:11 +053024#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
Marek Vasut7bb4fc32014-10-22 21:56:04 +020025#endif
26
Marek Vasut42066022014-10-22 21:55:58 +020027struct altera_spi_regs {
28 u32 rxdata;
29 u32 txdata;
30 u32 status;
31 u32 control;
32 u32 _reserved;
33 u32 slave_sel;
34};
Thomas Chou3a673f12010-04-30 11:34:16 +080035
Thomas Chouc5899542015-10-14 08:33:34 +080036struct altera_spi_platdata {
37 struct altera_spi_regs *regs;
38};
Thomas Chou3a673f12010-04-30 11:34:16 +080039
Thomas Chouc5899542015-10-14 08:33:34 +080040struct altera_spi_priv {
41 struct altera_spi_regs *regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080042};
Thomas Chou3a673f12010-04-30 11:34:16 +080043
Thomas Chouc5899542015-10-14 08:33:34 +080044static void spi_cs_activate(struct udevice *dev, uint cs)
Thomas Chou3a673f12010-04-30 11:34:16 +080045{
Thomas Chouc5899542015-10-14 08:33:34 +080046 struct udevice *bus = dev->parent;
47 struct altera_spi_priv *priv = dev_get_priv(bus);
48 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080049
Thomas Chouc5899542015-10-14 08:33:34 +080050 writel(1 << cs, &regs->slave_sel);
51 writel(ALTERA_SPI_CONTROL_SSO_MSK, &regs->control);
Thomas Chou3a673f12010-04-30 11:34:16 +080052}
53
Thomas Chouc5899542015-10-14 08:33:34 +080054static void spi_cs_deactivate(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080055{
Thomas Chouc5899542015-10-14 08:33:34 +080056 struct udevice *bus = dev->parent;
57 struct altera_spi_priv *priv = dev_get_priv(bus);
58 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080059
Thomas Chouc5899542015-10-14 08:33:34 +080060 writel(0, &regs->control);
61 writel(0, &regs->slave_sel);
Thomas Chou55be2b52010-12-27 09:30:17 +080062}
63
Thomas Chouc5899542015-10-14 08:33:34 +080064static int altera_spi_claim_bus(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080065{
Thomas Chouc5899542015-10-14 08:33:34 +080066 struct udevice *bus = dev->parent;
67 struct altera_spi_priv *priv = dev_get_priv(bus);
68 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080069
Thomas Chouc5899542015-10-14 08:33:34 +080070 writel(0, &regs->control);
71 writel(0, &regs->slave_sel);
Thomas Chou3a673f12010-04-30 11:34:16 +080072
Thomas Chouc5899542015-10-14 08:33:34 +080073 return 0;
Thomas Chou3a673f12010-04-30 11:34:16 +080074}
75
Thomas Chouc5899542015-10-14 08:33:34 +080076static int altera_spi_release_bus(struct udevice *dev)
Thomas Chou3a673f12010-04-30 11:34:16 +080077{
Thomas Chouc5899542015-10-14 08:33:34 +080078 struct udevice *bus = dev->parent;
79 struct altera_spi_priv *priv = dev_get_priv(bus);
80 struct altera_spi_regs *const regs = priv->regs;
Thomas Chou3a673f12010-04-30 11:34:16 +080081
Thomas Chouc5899542015-10-14 08:33:34 +080082 writel(0, &regs->slave_sel);
Thomas Chou3a673f12010-04-30 11:34:16 +080083
Thomas Chou3a673f12010-04-30 11:34:16 +080084 return 0;
85}
86
Thomas Chouc5899542015-10-14 08:33:34 +080087static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen,
88 const void *dout, void *din, unsigned long flags)
Thomas Chou3a673f12010-04-30 11:34:16 +080089{
Thomas Chouc5899542015-10-14 08:33:34 +080090 struct udevice *bus = dev->parent;
91 struct altera_spi_priv *priv = dev_get_priv(bus);
92 struct altera_spi_regs *const regs = priv->regs;
93 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
Thomas Chou3a673f12010-04-30 11:34:16 +080094
Thomas Chou3a673f12010-04-30 11:34:16 +080095 /* assume spi core configured to do 8 bit transfers */
Marek Vasut5c97e302014-10-22 21:56:02 +020096 unsigned int bytes = bitlen / 8;
97 const unsigned char *txp = dout;
98 unsigned char *rxp = din;
99 uint32_t reg, data, start;
Thomas Chou3a673f12010-04-30 11:34:16 +0800100
101 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
Thomas Chouc5899542015-10-14 08:33:34 +0800102 bus->seq, slave_plat->cs, bitlen, bytes, flags);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200103
Thomas Chou3a673f12010-04-30 11:34:16 +0800104 if (bitlen == 0)
105 goto done;
106
107 if (bitlen % 8) {
108 flags |= SPI_XFER_END;
109 goto done;
110 }
111
112 /* empty read buffer */
Thomas Chouc5899542015-10-14 08:33:34 +0800113 if (readl(&regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
114 readl(&regs->rxdata);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200115
Thomas Chou3a673f12010-04-30 11:34:16 +0800116 if (flags & SPI_XFER_BEGIN)
Thomas Chouc5899542015-10-14 08:33:34 +0800117 spi_cs_activate(dev, slave_plat->cs);
Thomas Chou3a673f12010-04-30 11:34:16 +0800118
119 while (bytes--) {
Marek Vasut5c97e302014-10-22 21:56:02 +0200120 if (txp)
121 data = *txp++;
122 else
123 data = CONFIG_ALTERA_SPI_IDLE_VAL;
Marek Vasuta49ffc32014-10-22 21:56:00 +0200124
Marek Vasut5c97e302014-10-22 21:56:02 +0200125 debug("%s: tx:%x ", __func__, data);
Thomas Chouc5899542015-10-14 08:33:34 +0800126 writel(data, &regs->txdata);
Marek Vasuta49ffc32014-10-22 21:56:00 +0200127
Marek Vasutec6938e2014-10-22 21:56:01 +0200128 start = get_timer(0);
129 while (1) {
Thomas Chouc5899542015-10-14 08:33:34 +0800130 reg = readl(&regs->status);
Marek Vasutec6938e2014-10-22 21:56:01 +0200131 if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
132 break;
133 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
Thomas Chouc5899542015-10-14 08:33:34 +0800134 debug("%s: Transmission timed out!\n", __func__);
135 return -1;
Marek Vasutec6938e2014-10-22 21:56:01 +0200136 }
137 }
Marek Vasuta49ffc32014-10-22 21:56:00 +0200138
Thomas Chouc5899542015-10-14 08:33:34 +0800139 data = readl(&regs->rxdata);
Thomas Chou3a673f12010-04-30 11:34:16 +0800140 if (rxp)
Marek Vasut5c97e302014-10-22 21:56:02 +0200141 *rxp++ = data & 0xff;
Marek Vasuta49ffc32014-10-22 21:56:00 +0200142
Marek Vasut5c97e302014-10-22 21:56:02 +0200143 debug("rx:%x\n", data);
Thomas Chou3a673f12010-04-30 11:34:16 +0800144 }
Marek Vasuta49ffc32014-10-22 21:56:00 +0200145
146done:
Thomas Chou3a673f12010-04-30 11:34:16 +0800147 if (flags & SPI_XFER_END)
Thomas Chouc5899542015-10-14 08:33:34 +0800148 spi_cs_deactivate(dev);
Thomas Chou3a673f12010-04-30 11:34:16 +0800149
150 return 0;
151}
Thomas Chouc5899542015-10-14 08:33:34 +0800152
153static int altera_spi_set_speed(struct udevice *bus, uint speed)
154{
155 return 0;
156}
157
158static int altera_spi_set_mode(struct udevice *bus, uint mode)
159{
160 return 0;
161}
162
163static int altera_spi_probe(struct udevice *bus)
164{
165 struct altera_spi_platdata *plat = dev_get_platdata(bus);
166 struct altera_spi_priv *priv = dev_get_priv(bus);
167
168 priv->regs = plat->regs;
169
170 return 0;
171}
172
173static int altera_spi_ofdata_to_platdata(struct udevice *bus)
174{
175 struct altera_spi_platdata *plat = dev_get_platdata(bus);
176
Thomas Chou3f1f1a22015-11-14 11:17:25 +0800177 plat->regs = map_physmem(dev_get_addr(bus),
178 sizeof(struct altera_spi_regs),
179 MAP_NOCACHE);
Thomas Chouc5899542015-10-14 08:33:34 +0800180
181 return 0;
182}
183
184static const struct dm_spi_ops altera_spi_ops = {
185 .claim_bus = altera_spi_claim_bus,
186 .release_bus = altera_spi_release_bus,
187 .xfer = altera_spi_xfer,
188 .set_speed = altera_spi_set_speed,
189 .set_mode = altera_spi_set_mode,
190 /*
191 * cs_info is not needed, since we require all chip selects to be
192 * in the device tree explicitly
193 */
194};
195
196static const struct udevice_id altera_spi_ids[] = {
Thomas Chouef4b3502015-10-31 20:55:48 +0800197 { .compatible = "altr,spi-1.0" },
198 {}
Thomas Chouc5899542015-10-14 08:33:34 +0800199};
200
201U_BOOT_DRIVER(altera_spi) = {
202 .name = "altera_spi",
203 .id = UCLASS_SPI,
204 .of_match = altera_spi_ids,
205 .ops = &altera_spi_ops,
206 .ofdata_to_platdata = altera_spi_ofdata_to_platdata,
207 .platdata_auto_alloc_size = sizeof(struct altera_spi_platdata),
208 .priv_auto_alloc_size = sizeof(struct altera_spi_priv),
209 .probe = altera_spi_probe,
210};