blob: 420bd25918450837e479d5031ca521e763cc2d09 [file] [log] [blame]
Yangbo Lu982f4252019-06-21 11:42:27 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4 * Copyright 2019 NXP Semiconductors
5 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13#include <config.h>
14#include <common.h>
15#include <command.h>
16#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -070017#include <cpu_func.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080018#include <errno.h>
19#include <hwconfig.h>
Simon Glass0f2af882020-05-10 11:40:05 -060020#include <log.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080021#include <mmc.h>
22#include <part.h>
Simon Glass274e0b02020-05-10 11:39:56 -060023#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060024#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070025#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060026#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060027#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070028#include <linux/err.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080029#include <power/regulator.h>
30#include <malloc.h>
31#include <fsl_esdhc_imx.h>
32#include <fdt_support.h>
33#include <asm/io.h>
34#include <dm.h>
35#include <asm-generic/gpio.h>
36#include <dm/pinctrl.h>
Walter Lozano8aff6732020-07-29 12:31:17 -030037#include <dt-structs.h>
38#include <mapmem.h>
39#include <dm/ofnode.h>
Haibo Chene6a999b2020-09-01 15:34:06 +080040#include <linux/iopoll.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080041
42#if !CONFIG_IS_ENABLED(BLK)
43#include "mmc_private.h"
44#endif
45
Haibo Chene8801ac2021-02-19 11:25:32 -080046#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
47#ifdef CONFIG_FSL_USDHC
48#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
49#endif
50#endif
51
Yangbo Lu982f4252019-06-21 11:42:27 +080052DECLARE_GLOBAL_DATA_PTR;
53
54#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
55 IRQSTATEN_CINT | \
56 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
57 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
58 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
59 IRQSTATEN_DINT)
60#define MAX_TUNING_LOOP 40
61#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
62
63struct fsl_esdhc {
64 uint dsaddr; /* SDMA system address register */
65 uint blkattr; /* Block attributes register */
66 uint cmdarg; /* Command argument register */
67 uint xfertyp; /* Transfer type register */
68 uint cmdrsp0; /* Command response 0 register */
69 uint cmdrsp1; /* Command response 1 register */
70 uint cmdrsp2; /* Command response 2 register */
71 uint cmdrsp3; /* Command response 3 register */
72 uint datport; /* Buffer data port register */
73 uint prsstat; /* Present state register */
74 uint proctl; /* Protocol control register */
75 uint sysctl; /* System Control Register */
76 uint irqstat; /* Interrupt status register */
77 uint irqstaten; /* Interrupt status enable register */
78 uint irqsigen; /* Interrupt signal enable register */
79 uint autoc12err; /* Auto CMD error status register */
80 uint hostcapblt; /* Host controller capabilities register */
81 uint wml; /* Watermark level register */
82 uint mixctrl; /* For USDHC */
83 char reserved1[4]; /* reserved */
84 uint fevt; /* Force event register */
85 uint admaes; /* ADMA error status register */
86 uint adsaddr; /* ADMA system address register */
87 char reserved2[4];
88 uint dllctrl;
89 uint dllstat;
90 uint clktunectrlstatus;
91 char reserved3[4];
92 uint strobe_dllctrl;
93 uint strobe_dllstat;
94 char reserved4[72];
95 uint vendorspec;
96 uint mmcboot;
97 uint vendorspec2;
Giulio Benetti65b5ec12020-01-10 15:51:46 +010098 uint tuning_ctrl; /* on i.MX6/7/8/RT */
Yangbo Lu982f4252019-06-21 11:42:27 +080099 char reserved5[44];
100 uint hostver; /* Host controller version register */
101 char reserved6[4]; /* reserved */
102 uint dmaerraddr; /* DMA error address register */
103 char reserved7[4]; /* reserved */
104 uint dmaerrattr; /* DMA error attribute register */
105 char reserved8[4]; /* reserved */
106 uint hostcapblt2; /* Host controller capabilities register 2 */
107 char reserved9[8]; /* reserved */
108 uint tcr; /* Tuning control register */
109 char reserved10[28]; /* reserved */
110 uint sddirctl; /* SD direction control register */
111 char reserved11[712];/* reserved */
112 uint scr; /* eSDHC control register */
113};
114
115struct fsl_esdhc_plat {
Walter Lozano8aff6732020-07-29 12:31:17 -0300116#if CONFIG_IS_ENABLED(OF_PLATDATA)
117 /* Put this first since driver model will copy the data here */
118 struct dtd_fsl_esdhc dtplat;
119#endif
120
Yangbo Lu982f4252019-06-21 11:42:27 +0800121 struct mmc_config cfg;
122 struct mmc mmc;
123};
124
125struct esdhc_soc_data {
126 u32 flags;
Yangbo Lu982f4252019-06-21 11:42:27 +0800127};
128
129/**
130 * struct fsl_esdhc_priv
131 *
132 * @esdhc_regs: registers of the sdhc controller
133 * @sdhc_clk: Current clk of the sdhc controller
134 * @bus_width: bus width, 1bit, 4bit or 8bit
135 * @cfg: mmc config
136 * @mmc: mmc
137 * Following is used when Driver Model is enabled for MMC
138 * @dev: pointer for the device
139 * @non_removable: 0: removable; 1: non-removable
Fabio Estevam7e3d8a92020-01-06 20:11:27 -0300140 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
Yangbo Lu982f4252019-06-21 11:42:27 +0800141 * @wp_enable: 1: enable checking wp; 0: no check
142 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
143 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
144 * @caps: controller capabilities
145 * @tuning_step: tuning step setting in tuning_ctrl register
146 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
147 * @strobe_dll_delay_target: settings in strobe_dllctrl
148 * @signal_voltage: indicating the current voltage
149 * @cd_gpio: gpio for card detection
150 * @wp_gpio: gpio for write protection
151 */
152struct fsl_esdhc_priv {
153 struct fsl_esdhc *esdhc_regs;
154 unsigned int sdhc_clk;
155 struct clk per_clk;
156 unsigned int clock;
157 unsigned int mode;
158 unsigned int bus_width;
159#if !CONFIG_IS_ENABLED(BLK)
160 struct mmc *mmc;
161#endif
162 struct udevice *dev;
163 int non_removable;
Fabio Estevam7e3d8a92020-01-06 20:11:27 -0300164 int broken_cd;
Yangbo Lu982f4252019-06-21 11:42:27 +0800165 int wp_enable;
166 int vs18_enable;
167 u32 flags;
168 u32 caps;
169 u32 tuning_step;
170 u32 tuning_start_tap;
171 u32 strobe_dll_delay_target;
172 u32 signal_voltage;
Ye Li7aa20fd2019-07-11 03:29:02 +0000173#if CONFIG_IS_ENABLED(DM_REGULATOR)
Yangbo Lu982f4252019-06-21 11:42:27 +0800174 struct udevice *vqmmc_dev;
175 struct udevice *vmmc_dev;
176#endif
Simon Glassfa4689a2019-12-06 21:41:35 -0700177#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lu982f4252019-06-21 11:42:27 +0800178 struct gpio_desc cd_gpio;
179 struct gpio_desc wp_gpio;
180#endif
181};
182
183/* Return the XFERTYP flags for a given command and data packet */
184static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
185{
186 uint xfertyp = 0;
187
188 if (data) {
189 xfertyp |= XFERTYP_DPSEL;
190#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
191 xfertyp |= XFERTYP_DMAEN;
192#endif
193 if (data->blocks > 1) {
194 xfertyp |= XFERTYP_MSBSEL;
195 xfertyp |= XFERTYP_BCEN;
196#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
197 xfertyp |= XFERTYP_AC12EN;
198#endif
199 }
200
201 if (data->flags & MMC_DATA_READ)
202 xfertyp |= XFERTYP_DTDSEL;
203 }
204
205 if (cmd->resp_type & MMC_RSP_CRC)
206 xfertyp |= XFERTYP_CCCEN;
207 if (cmd->resp_type & MMC_RSP_OPCODE)
208 xfertyp |= XFERTYP_CICEN;
209 if (cmd->resp_type & MMC_RSP_136)
210 xfertyp |= XFERTYP_RSPTYP_136;
211 else if (cmd->resp_type & MMC_RSP_BUSY)
212 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
213 else if (cmd->resp_type & MMC_RSP_PRESENT)
214 xfertyp |= XFERTYP_RSPTYP_48;
215
216 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
217 xfertyp |= XFERTYP_CMDTYP_ABORT;
218
219 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
220}
221
222#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
223/*
224 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
225 */
226static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
227 struct mmc_data *data)
228{
229 struct fsl_esdhc *regs = priv->esdhc_regs;
230 uint blocks;
231 char *buffer;
232 uint databuf;
233 uint size;
234 uint irqstat;
235 ulong start;
236
237 if (data->flags & MMC_DATA_READ) {
238 blocks = data->blocks;
239 buffer = data->dest;
240 while (blocks) {
241 start = get_timer(0);
242 size = data->blocksize;
243 irqstat = esdhc_read32(&regs->irqstat);
244 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
245 if (get_timer(start) > PIO_TIMEOUT) {
246 printf("\nData Read Failed in PIO Mode.");
247 return;
248 }
249 }
250 while (size && (!(irqstat & IRQSTAT_TC))) {
251 udelay(100); /* Wait before last byte transfer complete */
252 irqstat = esdhc_read32(&regs->irqstat);
253 databuf = in_le32(&regs->datport);
254 *((uint *)buffer) = databuf;
255 buffer += 4;
256 size -= 4;
257 }
258 blocks--;
259 }
260 } else {
261 blocks = data->blocks;
262 buffer = (char *)data->src;
263 while (blocks) {
264 start = get_timer(0);
265 size = data->blocksize;
266 irqstat = esdhc_read32(&regs->irqstat);
267 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
268 if (get_timer(start) > PIO_TIMEOUT) {
269 printf("\nData Write Failed in PIO Mode.");
270 return;
271 }
272 }
273 while (size && (!(irqstat & IRQSTAT_TC))) {
274 udelay(100); /* Wait before last byte transfer complete */
275 databuf = *((uint *)buffer);
276 buffer += 4;
277 size -= 4;
278 irqstat = esdhc_read32(&regs->irqstat);
279 out_le32(&regs->datport, databuf);
280 }
281 blocks--;
282 }
283 }
284}
285#endif
286
287static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
288 struct mmc_data *data)
289{
290 int timeout;
291 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu16b38542019-06-21 11:42:30 +0800292#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lu982f4252019-06-21 11:42:27 +0800293 dma_addr_t addr;
294#endif
295 uint wml_value;
296
297 wml_value = data->blocksize/4;
298
299 if (data->flags & MMC_DATA_READ) {
300 if (wml_value > WML_RD_WML_MAX)
301 wml_value = WML_RD_WML_MAX_VAL;
302
303 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
304#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Yangbo Lu16b38542019-06-21 11:42:30 +0800305#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lu982f4252019-06-21 11:42:27 +0800306 addr = virt_to_phys((void *)(data->dest));
307 if (upper_32_bits(addr))
308 printf("Error found for upper 32 bits\n");
309 else
310 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
311#else
312 esdhc_write32(&regs->dsaddr, (u32)data->dest);
313#endif
314#endif
315 } else {
316#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
317 flush_dcache_range((ulong)data->src,
318 (ulong)data->src+data->blocks
319 *data->blocksize);
320#endif
321 if (wml_value > WML_WR_WML_MAX)
322 wml_value = WML_WR_WML_MAX_VAL;
323 if (priv->wp_enable) {
324 if ((esdhc_read32(&regs->prsstat) &
325 PRSSTAT_WPSPL) == 0) {
326 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
327 return -ETIMEDOUT;
328 }
329 } else {
Simon Glassfa4689a2019-12-06 21:41:35 -0700330#if CONFIG_IS_ENABLED(DM_GPIO)
331 if (dm_gpio_is_valid(&priv->wp_gpio) &&
332 dm_gpio_get_value(&priv->wp_gpio)) {
Yangbo Lu982f4252019-06-21 11:42:27 +0800333 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
334 return -ETIMEDOUT;
335 }
336#endif
337 }
338
339 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
340 wml_value << 16);
341#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Yangbo Lu16b38542019-06-21 11:42:30 +0800342#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lu982f4252019-06-21 11:42:27 +0800343 addr = virt_to_phys((void *)(data->src));
344 if (upper_32_bits(addr))
345 printf("Error found for upper 32 bits\n");
346 else
347 esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
348#else
349 esdhc_write32(&regs->dsaddr, (u32)data->src);
350#endif
351#endif
352 }
353
354 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
355
356 /* Calculate the timeout period for data transactions */
357 /*
358 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
359 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
360 * So, Number of SD Clock cycles for 0.25sec should be minimum
361 * (SD Clock/sec * 0.25 sec) SD Clock cycles
362 * = (mmc->clock * 1/4) SD Clock cycles
363 * As 1) >= 2)
364 * => (2^(timeout+13)) >= mmc->clock * 1/4
365 * Taking log2 both the sides
366 * => timeout + 13 >= log2(mmc->clock/4)
367 * Rounding up to next power of 2
368 * => timeout + 13 = log2(mmc->clock/4) + 1
369 * => timeout + 13 = fls(mmc->clock/4)
370 *
371 * However, the MMC spec "It is strongly recommended for hosts to
372 * implement more than 500ms timeout value even if the card
373 * indicates the 250ms maximum busy length." Even the previous
374 * value of 300ms is known to be insufficient for some cards.
375 * So, we use
376 * => timeout + 13 = fls(mmc->clock/2)
377 */
378 timeout = fls(mmc->clock/2);
379 timeout -= 13;
380
381 if (timeout > 14)
382 timeout = 14;
383
384 if (timeout < 0)
385 timeout = 0;
386
387#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
388 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
389 timeout++;
390#endif
391
392#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
393 timeout = 0xE;
394#endif
395 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
396
397 return 0;
398}
399
400static void check_and_invalidate_dcache_range
401 (struct mmc_cmd *cmd,
402 struct mmc_data *data) {
403 unsigned start = 0;
404 unsigned end = 0;
405 unsigned size = roundup(ARCH_DMA_MINALIGN,
406 data->blocks*data->blocksize);
Yangbo Lu16b38542019-06-21 11:42:30 +0800407#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
Yangbo Lu982f4252019-06-21 11:42:27 +0800408 dma_addr_t addr;
409
410 addr = virt_to_phys((void *)(data->dest));
411 if (upper_32_bits(addr))
412 printf("Error found for upper 32 bits\n");
413 else
414 start = lower_32_bits(addr);
415#else
416 start = (unsigned)data->dest;
417#endif
418 end = start + size;
419 invalidate_dcache_range(start, end);
420}
421
422#ifdef CONFIG_MCF5441x
423/*
424 * Swaps 32-bit words to little-endian byte order.
425 */
426static inline void sd_swap_dma_buff(struct mmc_data *data)
427{
428 int i, size = data->blocksize >> 2;
429 u32 *buffer = (u32 *)data->dest;
430 u32 sw;
431
432 while (data->blocks--) {
433 for (i = 0; i < size; i++) {
434 sw = __sw32(*buffer);
435 *buffer++ = sw;
436 }
437 }
438}
439#endif
440
441/*
442 * Sends a command out on the bus. Takes the mmc pointer,
443 * a command pointer, and an optional data pointer.
444 */
445static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
446 struct mmc_cmd *cmd, struct mmc_data *data)
447{
448 int err = 0;
449 uint xfertyp;
450 uint irqstat;
451 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
452 struct fsl_esdhc *regs = priv->esdhc_regs;
453 unsigned long start;
454
455#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
456 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
457 return 0;
458#endif
459
460 esdhc_write32(&regs->irqstat, -1);
461
462 sync();
463
464 /* Wait for the bus to be idle */
465 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
466 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
467 ;
468
469 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
470 ;
471
Yangbo Lu982f4252019-06-21 11:42:27 +0800472 /* Set up for a data transfer if we have one */
473 if (data) {
474 err = esdhc_setup_data(priv, mmc, data);
475 if(err)
476 return err;
477
478 if (data->flags & MMC_DATA_READ)
479 check_and_invalidate_dcache_range(cmd, data);
480 }
481
482 /* Figure out the transfer arguments */
483 xfertyp = esdhc_xfertyp(cmd, data);
484
485 /* Mask all irqs */
486 esdhc_write32(&regs->irqsigen, 0);
487
488 /* Send the command */
489 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
490#if defined(CONFIG_FSL_USDHC)
491 esdhc_write32(&regs->mixctrl,
492 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
493 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
494 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
495#else
496 esdhc_write32(&regs->xfertyp, xfertyp);
497#endif
498
499 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
500 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
501 flags = IRQSTAT_BRR;
502
503 /* Wait for the command to complete */
504 start = get_timer(0);
505 while (!(esdhc_read32(&regs->irqstat) & flags)) {
506 if (get_timer(start) > 1000) {
507 err = -ETIMEDOUT;
508 goto out;
509 }
510 }
511
512 irqstat = esdhc_read32(&regs->irqstat);
513
514 if (irqstat & CMD_ERR) {
515 err = -ECOMM;
516 goto out;
517 }
518
519 if (irqstat & IRQSTAT_CTOE) {
520 err = -ETIMEDOUT;
521 goto out;
522 }
523
524 /* Switch voltage to 1.8V if CMD11 succeeded */
525 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
526 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
527
528 printf("Run CMD11 1.8V switch\n");
529 /* Sleep for 5 ms - max time for card to switch to 1.8V */
530 udelay(5000);
531 }
532
533 /* Workaround for ESDHC errata ENGcm03648 */
534 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Peng Fan3dbea592019-07-10 09:35:30 +0000535 int timeout = 50000;
Yangbo Lu982f4252019-06-21 11:42:27 +0800536
Peng Fan3dbea592019-07-10 09:35:30 +0000537 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
Yangbo Lu982f4252019-06-21 11:42:27 +0800538 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
539 PRSSTAT_DAT0)) {
540 udelay(100);
541 timeout--;
542 }
543
544 if (timeout <= 0) {
545 printf("Timeout waiting for DAT0 to go high!\n");
546 err = -ETIMEDOUT;
547 goto out;
548 }
549 }
550
551 /* Copy the response to the response buffer */
552 if (cmd->resp_type & MMC_RSP_136) {
553 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
554
555 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
556 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
557 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
558 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
559 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
560 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
561 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
562 cmd->response[3] = (cmdrsp0 << 8);
563 } else
564 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
565
566 /* Wait until all of the blocks are transferred */
567 if (data) {
568#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
569 esdhc_pio_read_write(priv, data);
570#else
571 flags = DATA_COMPLETE;
572 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
573 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
574 flags = IRQSTAT_BRR;
575 }
576
577 do {
578 irqstat = esdhc_read32(&regs->irqstat);
579
580 if (irqstat & IRQSTAT_DTOE) {
581 err = -ETIMEDOUT;
582 goto out;
583 }
584
585 if (irqstat & DATA_ERR) {
586 err = -ECOMM;
587 goto out;
588 }
589 } while ((irqstat & flags) != flags);
590
591 /*
592 * Need invalidate the dcache here again to avoid any
593 * cache-fill during the DMA operations such as the
594 * speculative pre-fetching etc.
595 */
596 if (data->flags & MMC_DATA_READ) {
597 check_and_invalidate_dcache_range(cmd, data);
598#ifdef CONFIG_MCF5441x
599 sd_swap_dma_buff(data);
600#endif
601 }
602#endif
603 }
604
605out:
606 /* Reset CMD and DATA portions on error */
607 if (err) {
608 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
609 SYSCTL_RSTC);
610 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
611 ;
612
613 if (data) {
614 esdhc_write32(&regs->sysctl,
615 esdhc_read32(&regs->sysctl) |
616 SYSCTL_RSTD);
617 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
618 ;
619 }
620
621 /* If this was CMD11, then notify that power cycle is needed */
622 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
623 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
624 }
625
626 esdhc_write32(&regs->irqstat, -1);
627
628 return err;
629}
630
631static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
632{
633 struct fsl_esdhc *regs = priv->esdhc_regs;
634 int div = 1;
Haibo Chene6a999b2020-09-01 15:34:06 +0800635 u32 tmp;
636 int ret;
Yangbo Lu982f4252019-06-21 11:42:27 +0800637#ifdef ARCH_MXC
638#ifdef CONFIG_MX53
639 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
640 int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
641#else
642 int pre_div = 1;
643#endif
644#else
645 int pre_div = 2;
646#endif
647 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
648 int sdhc_clk = priv->sdhc_clk;
649 uint clk;
650
Yangbo Lu982f4252019-06-21 11:42:27 +0800651 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
652 pre_div *= 2;
653
654 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
655 div++;
656
657 pre_div >>= 1;
658 div -= 1;
659
660 clk = (pre_div << 8) | (div << 4);
661
662#ifdef CONFIG_FSL_USDHC
Haibo Chen7818a812021-03-03 17:05:46 +0800663 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
664 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
665 if (ret)
666 pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
Yangbo Lu982f4252019-06-21 11:42:27 +0800667#else
668 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
669#endif
670
671 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
672
Haibo Chene6a999b2020-09-01 15:34:06 +0800673 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
674 if (ret)
675 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
Yangbo Lu982f4252019-06-21 11:42:27 +0800676
677#ifdef CONFIG_FSL_USDHC
Haibo Chen7818a812021-03-03 17:05:46 +0800678 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
Yangbo Lu982f4252019-06-21 11:42:27 +0800679#else
680 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
681#endif
682
683 priv->clock = clock;
684}
685
Yangbo Lu982f4252019-06-21 11:42:27 +0800686#ifdef MMC_SUPPORTS_TUNING
687static int esdhc_change_pinstate(struct udevice *dev)
688{
689 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
690 int ret;
691
692 switch (priv->mode) {
693 case UHS_SDR50:
694 case UHS_DDR50:
695 ret = pinctrl_select_state(dev, "state_100mhz");
696 break;
697 case UHS_SDR104:
698 case MMC_HS_200:
699 case MMC_HS_400:
Peng Fan69b9d3a2019-07-10 09:35:26 +0000700 case MMC_HS_400_ES:
Yangbo Lu982f4252019-06-21 11:42:27 +0800701 ret = pinctrl_select_state(dev, "state_200mhz");
702 break;
703 default:
704 ret = pinctrl_select_state(dev, "default");
705 break;
706 }
707
708 if (ret)
709 printf("%s %d error\n", __func__, priv->mode);
710
711 return ret;
712}
713
714static void esdhc_reset_tuning(struct mmc *mmc)
715{
716 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
717 struct fsl_esdhc *regs = priv->esdhc_regs;
718
719 if (priv->flags & ESDHC_FLAG_USDHC) {
720 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
721 esdhc_clrbits32(&regs->autoc12err,
722 MIX_CTRL_SMPCLK_SEL |
723 MIX_CTRL_EXE_TUNE);
724 }
725 }
726}
727
728static void esdhc_set_strobe_dll(struct mmc *mmc)
729{
730 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
731 struct fsl_esdhc *regs = priv->esdhc_regs;
732 u32 val;
Haibo Chen7818a812021-03-03 17:05:46 +0800733 u32 tmp;
734 int ret;
Yangbo Lu982f4252019-06-21 11:42:27 +0800735
736 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
Haibo Chen7818a812021-03-03 17:05:46 +0800737 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
738 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
739 if (ret)
740 pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
Haibo Chen920f5d02020-09-30 15:52:23 +0800741 esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
Yangbo Lu982f4252019-06-21 11:42:27 +0800742
743 /*
744 * enable strobe dll ctrl and adjust the delay target
745 * for the uSDHC loopback read clock
746 */
747 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
748 (priv->strobe_dll_delay_target <<
749 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
Haibo Chen920f5d02020-09-30 15:52:23 +0800750 esdhc_write32(&regs->strobe_dllctrl, val);
Yangbo Lu982f4252019-06-21 11:42:27 +0800751 /* wait 1us to make sure strobe dll status register stable */
752 mdelay(1);
Haibo Chen920f5d02020-09-30 15:52:23 +0800753 val = esdhc_read32(&regs->strobe_dllstat);
Yangbo Lu982f4252019-06-21 11:42:27 +0800754 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
755 pr_warn("HS400 strobe DLL status REF not lock!\n");
756 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
757 pr_warn("HS400 strobe DLL status SLV not lock!\n");
Haibo Chen7818a812021-03-03 17:05:46 +0800758 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
Yangbo Lu982f4252019-06-21 11:42:27 +0800759 }
760}
761
762static int esdhc_set_timing(struct mmc *mmc)
763{
764 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
765 struct fsl_esdhc *regs = priv->esdhc_regs;
766 u32 mixctrl;
767
Haibo Chen920f5d02020-09-30 15:52:23 +0800768 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800769 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
770
771 switch (mmc->selected_mode) {
772 case MMC_LEGACY:
Yangbo Lu982f4252019-06-21 11:42:27 +0800773 esdhc_reset_tuning(mmc);
Haibo Chen920f5d02020-09-30 15:52:23 +0800774 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800775 break;
776 case MMC_HS_400:
Peng Fan69b9d3a2019-07-10 09:35:26 +0000777 case MMC_HS_400_ES:
Yangbo Lu982f4252019-06-21 11:42:27 +0800778 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
Haibo Chen920f5d02020-09-30 15:52:23 +0800779 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800780 break;
781 case MMC_HS:
782 case MMC_HS_52:
783 case MMC_HS_200:
784 case SD_HS:
785 case UHS_SDR12:
786 case UHS_SDR25:
787 case UHS_SDR50:
788 case UHS_SDR104:
Haibo Chen920f5d02020-09-30 15:52:23 +0800789 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800790 break;
791 case UHS_DDR50:
792 case MMC_DDR_52:
793 mixctrl |= MIX_CTRL_DDREN;
Haibo Chen920f5d02020-09-30 15:52:23 +0800794 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800795 break;
796 default:
797 printf("Not supported %d\n", mmc->selected_mode);
798 return -EINVAL;
799 }
800
801 priv->mode = mmc->selected_mode;
802
803 return esdhc_change_pinstate(mmc->dev);
804}
805
806static int esdhc_set_voltage(struct mmc *mmc)
807{
808 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
809 struct fsl_esdhc *regs = priv->esdhc_regs;
Heiko Schocher7989f602021-01-15 10:37:09 +0100810#if CONFIG_IS_ENABLED(DM_REGULATOR)
Yangbo Lu982f4252019-06-21 11:42:27 +0800811 int ret;
Heiko Schocher7989f602021-01-15 10:37:09 +0100812#endif
Yangbo Lu982f4252019-06-21 11:42:27 +0800813
814 priv->signal_voltage = mmc->signal_voltage;
815 switch (mmc->signal_voltage) {
816 case MMC_SIGNAL_VOLTAGE_330:
817 if (priv->vs18_enable)
Marek Vasutba79fed2020-05-22 18:28:33 +0200818 return -ENOTSUPP;
Yangbo Lu982f4252019-06-21 11:42:27 +0800819#if CONFIG_IS_ENABLED(DM_REGULATOR)
820 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
821 ret = regulator_set_value(priv->vqmmc_dev, 3300000);
822 if (ret) {
823 printf("Setting to 3.3V error");
824 return -EIO;
825 }
826 /* Wait for 5ms */
827 mdelay(5);
828 }
829#endif
830
831 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
832 if (!(esdhc_read32(&regs->vendorspec) &
833 ESDHC_VENDORSPEC_VSELECT))
834 return 0;
835
836 return -EAGAIN;
837 case MMC_SIGNAL_VOLTAGE_180:
838#if CONFIG_IS_ENABLED(DM_REGULATOR)
839 if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
840 ret = regulator_set_value(priv->vqmmc_dev, 1800000);
841 if (ret) {
842 printf("Setting to 1.8V error");
843 return -EIO;
844 }
845 }
846#endif
847 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
848 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
849 return 0;
850
851 return -EAGAIN;
852 case MMC_SIGNAL_VOLTAGE_120:
853 return -ENOTSUPP;
854 default:
855 return 0;
856 }
857}
858
859static void esdhc_stop_tuning(struct mmc *mmc)
860{
861 struct mmc_cmd cmd;
862
863 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
864 cmd.cmdarg = 0;
865 cmd.resp_type = MMC_RSP_R1b;
866
867 dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
868}
869
870static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
871{
Simon Glassfa20e932020-12-03 16:55:20 -0700872 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +0800873 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
874 struct fsl_esdhc *regs = priv->esdhc_regs;
875 struct mmc *mmc = &plat->mmc;
Haibo Chen920f5d02020-09-30 15:52:23 +0800876 u32 irqstaten = esdhc_read32(&regs->irqstaten);
877 u32 irqsigen = esdhc_read32(&regs->irqsigen);
Yangbo Lu982f4252019-06-21 11:42:27 +0800878 int i, ret = -ETIMEDOUT;
879 u32 val, mixctrl;
880
881 /* clock tuning is not needed for upto 52MHz */
882 if (mmc->clock <= 52000000)
883 return 0;
884
885 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
886 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chen920f5d02020-09-30 15:52:23 +0800887 val = esdhc_read32(&regs->autoc12err);
888 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800889 val &= ~MIX_CTRL_SMPCLK_SEL;
890 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
891
892 val |= MIX_CTRL_EXE_TUNE;
893 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
894
Haibo Chen920f5d02020-09-30 15:52:23 +0800895 esdhc_write32(&regs->autoc12err, val);
896 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800897 }
898
899 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
Haibo Chen920f5d02020-09-30 15:52:23 +0800900 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800901 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
Haibo Chen920f5d02020-09-30 15:52:23 +0800902 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800903
Haibo Chen920f5d02020-09-30 15:52:23 +0800904 esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
905 esdhc_write32(&regs->irqsigen, IRQSTATEN_BRR);
Yangbo Lu982f4252019-06-21 11:42:27 +0800906
907 /*
908 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
909 * of loops reaches 40 times.
910 */
911 for (i = 0; i < MAX_TUNING_LOOP; i++) {
912 u32 ctrl;
913
914 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
915 if (mmc->bus_width == 8)
Haibo Chen920f5d02020-09-30 15:52:23 +0800916 esdhc_write32(&regs->blkattr, 0x7080);
Yangbo Lu982f4252019-06-21 11:42:27 +0800917 else if (mmc->bus_width == 4)
Haibo Chen920f5d02020-09-30 15:52:23 +0800918 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lu982f4252019-06-21 11:42:27 +0800919 } else {
Haibo Chen920f5d02020-09-30 15:52:23 +0800920 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lu982f4252019-06-21 11:42:27 +0800921 }
922
923 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
Haibo Chen920f5d02020-09-30 15:52:23 +0800924 val = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800925 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
Haibo Chen920f5d02020-09-30 15:52:23 +0800926 esdhc_write32(&regs->mixctrl, val);
Yangbo Lu982f4252019-06-21 11:42:27 +0800927
928 /* We are using STD tuning, no need to check return value */
929 mmc_send_tuning(mmc, opcode, NULL);
930
Haibo Chen920f5d02020-09-30 15:52:23 +0800931 ctrl = esdhc_read32(&regs->autoc12err);
Yangbo Lu982f4252019-06-21 11:42:27 +0800932 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
933 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
Yangbo Lu982f4252019-06-21 11:42:27 +0800934 ret = 0;
935 break;
936 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800937 }
938
Haibo Chen920f5d02020-09-30 15:52:23 +0800939 esdhc_write32(&regs->irqstaten, irqstaten);
940 esdhc_write32(&regs->irqsigen, irqsigen);
Yangbo Lu982f4252019-06-21 11:42:27 +0800941
942 esdhc_stop_tuning(mmc);
943
944 return ret;
945}
946#endif
947
948static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
949{
950 struct fsl_esdhc *regs = priv->esdhc_regs;
951 int ret __maybe_unused;
Peng Fan2cdf52b2019-11-04 17:14:15 +0800952 u32 clock;
Yangbo Lu982f4252019-06-21 11:42:27 +0800953
Haibo Cheneaa2f102020-11-03 17:18:35 +0800954#ifdef MMC_SUPPORTS_TUNING
955 /*
956 * call esdhc_set_timing() before update the clock rate,
957 * This is because current we support DDR and SDR mode,
958 * Once the DDR_EN bit is set, the card clock will be
959 * divide by 2 automatically. So need to do this before
960 * setting clock rate.
961 */
962 if (priv->mode != mmc->selected_mode) {
963 ret = esdhc_set_timing(mmc);
964 if (ret) {
965 printf("esdhc_set_timing error %d\n", ret);
966 return ret;
967 }
968 }
969#endif
970
Yangbo Lu982f4252019-06-21 11:42:27 +0800971 /* Set the clock speed */
Peng Fan2cdf52b2019-11-04 17:14:15 +0800972 clock = mmc->clock;
973 if (clock < mmc->cfg->f_min)
974 clock = mmc->cfg->f_min;
975
976 if (priv->clock != clock)
977 set_sysctl(priv, mmc, clock);
Yangbo Lu982f4252019-06-21 11:42:27 +0800978
979#ifdef MMC_SUPPORTS_TUNING
980 if (mmc->clk_disable) {
981#ifdef CONFIG_FSL_USDHC
Haibo Chen7818a812021-03-03 17:05:46 +0800982 u32 tmp;
983
984 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
985 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
986 if (ret)
987 pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
Yangbo Lu982f4252019-06-21 11:42:27 +0800988#else
989 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
990#endif
991 } else {
992#ifdef CONFIG_FSL_USDHC
Haibo Chen7818a812021-03-03 17:05:46 +0800993 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
Yangbo Lu982f4252019-06-21 11:42:27 +0800994#else
995 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
996#endif
997 }
998
Haibo Cheneaa2f102020-11-03 17:18:35 +0800999 /*
1000 * For HS400/HS400ES mode, make sure set the strobe dll in the
1001 * target clock rate. So call esdhc_set_strobe_dll() after the
1002 * clock updated.
1003 */
1004 if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
1005 esdhc_set_strobe_dll(mmc);
Yangbo Lu982f4252019-06-21 11:42:27 +08001006
1007 if (priv->signal_voltage != mmc->signal_voltage) {
1008 ret = esdhc_set_voltage(mmc);
1009 if (ret) {
Marek Vasutba79fed2020-05-22 18:28:33 +02001010 if (ret != -ENOTSUPP)
1011 printf("esdhc_set_voltage error %d\n", ret);
Yangbo Lu982f4252019-06-21 11:42:27 +08001012 return ret;
1013 }
1014 }
1015#endif
1016
1017 /* Set the bus width */
1018 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1019
1020 if (mmc->bus_width == 4)
1021 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
1022 else if (mmc->bus_width == 8)
1023 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
1024
1025 return 0;
1026}
1027
1028static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1029{
1030 struct fsl_esdhc *regs = priv->esdhc_regs;
1031 ulong start;
1032
1033 /* Reset the entire host controller */
1034 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1035
1036 /* Wait until the controller is available */
1037 start = get_timer(0);
1038 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1039 if (get_timer(start) > 1000)
1040 return -ETIMEDOUT;
1041 }
1042
1043#if defined(CONFIG_FSL_USDHC)
1044 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1045 esdhc_write32(&regs->mmcboot, 0x0);
1046 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1047 esdhc_write32(&regs->mixctrl, 0x0);
1048 esdhc_write32(&regs->clktunectrlstatus, 0x0);
1049
1050 /* Put VEND_SPEC to default value */
1051 if (priv->vs18_enable)
1052 esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
1053 ESDHC_VENDORSPEC_VSELECT));
1054 else
1055 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
1056
1057 /* Disable DLL_CTRL delay line */
1058 esdhc_write32(&regs->dllctrl, 0x0);
1059#endif
1060
1061#ifndef ARCH_MXC
1062 /* Enable cache snooping */
1063 esdhc_write32(&regs->scr, 0x00000040);
1064#endif
1065
1066#ifndef CONFIG_FSL_USDHC
1067 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1068#else
Haibo Chen7818a812021-03-03 17:05:46 +08001069 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
Yangbo Lu982f4252019-06-21 11:42:27 +08001070#endif
1071
1072 /* Set the initial clock speed */
1073 mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1074
1075 /* Disable the BRR and BWR bits in IRQSTAT */
1076 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1077
1078#ifdef CONFIG_MCF5441x
1079 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1080#else
1081 /* Put the PROCTL reg back to the default */
1082 esdhc_write32(&regs->proctl, PROCTL_INIT);
1083#endif
1084
1085 /* Set timout to the maximum value */
1086 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1087
1088 return 0;
1089}
1090
1091static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1092{
1093 struct fsl_esdhc *regs = priv->esdhc_regs;
1094 int timeout = 1000;
1095
1096#ifdef CONFIG_ESDHC_DETECT_QUIRK
1097 if (CONFIG_ESDHC_DETECT_QUIRK)
1098 return 1;
1099#endif
1100
1101#if CONFIG_IS_ENABLED(DM_MMC)
1102 if (priv->non_removable)
1103 return 1;
Fabio Estevam7e3d8a92020-01-06 20:11:27 -03001104
1105 if (priv->broken_cd)
1106 return 1;
Simon Glassfa4689a2019-12-06 21:41:35 -07001107#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lu982f4252019-06-21 11:42:27 +08001108 if (dm_gpio_is_valid(&priv->cd_gpio))
1109 return dm_gpio_get_value(&priv->cd_gpio);
1110#endif
1111#endif
1112
1113 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1114 udelay(1000);
1115
1116 return timeout > 0;
1117}
1118
1119static int esdhc_reset(struct fsl_esdhc *regs)
1120{
1121 ulong start;
1122
1123 /* reset the controller */
1124 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1125
1126 /* hardware clears the bit when it is done */
1127 start = get_timer(0);
1128 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1129 if (get_timer(start) > 100) {
1130 printf("MMC/SD: Reset never completed.\n");
1131 return -ETIMEDOUT;
1132 }
1133 }
1134
1135 return 0;
1136}
1137
1138#if !CONFIG_IS_ENABLED(DM_MMC)
1139static int esdhc_getcd(struct mmc *mmc)
1140{
1141 struct fsl_esdhc_priv *priv = mmc->priv;
1142
1143 return esdhc_getcd_common(priv);
1144}
1145
1146static int esdhc_init(struct mmc *mmc)
1147{
1148 struct fsl_esdhc_priv *priv = mmc->priv;
1149
1150 return esdhc_init_common(priv, mmc);
1151}
1152
1153static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1154 struct mmc_data *data)
1155{
1156 struct fsl_esdhc_priv *priv = mmc->priv;
1157
1158 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1159}
1160
1161static int esdhc_set_ios(struct mmc *mmc)
1162{
1163 struct fsl_esdhc_priv *priv = mmc->priv;
1164
1165 return esdhc_set_ios_common(priv, mmc);
1166}
1167
1168static const struct mmc_ops esdhc_ops = {
1169 .getcd = esdhc_getcd,
1170 .init = esdhc_init,
1171 .send_cmd = esdhc_send_cmd,
1172 .set_ios = esdhc_set_ios,
1173};
1174#endif
1175
1176static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1177 struct fsl_esdhc_plat *plat)
1178{
1179 struct mmc_config *cfg;
1180 struct fsl_esdhc *regs;
1181 u32 caps, voltage_caps;
1182 int ret;
1183
1184 if (!priv)
1185 return -EINVAL;
1186
1187 regs = priv->esdhc_regs;
1188
1189 /* First reset the eSDHC controller */
1190 ret = esdhc_reset(regs);
1191 if (ret)
1192 return ret;
1193
1194#ifdef CONFIG_MCF5441x
1195 /* ColdFire, using SDHC_DATA[3] for card detection */
1196 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1197#endif
1198
1199#ifndef CONFIG_FSL_USDHC
1200 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1201 | SYSCTL_IPGEN | SYSCTL_CKEN);
1202 /* Clearing tuning bits in case ROM has set it already */
1203 esdhc_write32(&regs->mixctrl, 0);
1204 esdhc_write32(&regs->autoc12err, 0);
1205 esdhc_write32(&regs->clktunectrlstatus, 0);
1206#else
Haibo Chen7818a812021-03-03 17:05:46 +08001207 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
Yangbo Lu982f4252019-06-21 11:42:27 +08001208#endif
1209
1210 if (priv->vs18_enable)
1211 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1212
Haibo Chen920f5d02020-09-30 15:52:23 +08001213 esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
Yangbo Lu982f4252019-06-21 11:42:27 +08001214 cfg = &plat->cfg;
1215#ifndef CONFIG_DM_MMC
1216 memset(cfg, '\0', sizeof(*cfg));
1217#endif
1218
1219 voltage_caps = 0;
1220 caps = esdhc_read32(&regs->hostcapblt);
1221
1222#ifdef CONFIG_MCF5441x
1223 /*
1224 * MCF5441x RM declares in more points that sdhc clock speed must
1225 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1226 * from host capabilities.
1227 */
1228 caps &= ~ESDHC_HOSTCAPBLT_HSS;
1229#endif
1230
1231#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1232 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1233 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1234#endif
1235
1236/* T4240 host controller capabilities register should have VS33 bit */
1237#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1238 caps = caps | ESDHC_HOSTCAPBLT_VS33;
1239#endif
1240
1241 if (caps & ESDHC_HOSTCAPBLT_VS18)
1242 voltage_caps |= MMC_VDD_165_195;
1243 if (caps & ESDHC_HOSTCAPBLT_VS30)
1244 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1245 if (caps & ESDHC_HOSTCAPBLT_VS33)
1246 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1247
1248 cfg->name = "FSL_SDHC";
1249#if !CONFIG_IS_ENABLED(DM_MMC)
1250 cfg->ops = &esdhc_ops;
1251#endif
1252#ifdef CONFIG_SYS_SD_VOLTAGE
1253 cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1254#else
1255 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1256#endif
1257 if ((cfg->voltages & voltage_caps) == 0) {
1258 printf("voltage not supported by controller\n");
1259 return -1;
1260 }
1261
1262 if (priv->bus_width == 8)
1263 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1264 else if (priv->bus_width == 4)
1265 cfg->host_caps = MMC_MODE_4BIT;
1266
1267 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1268#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1269 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1270#endif
1271
1272 if (priv->bus_width > 0) {
1273 if (priv->bus_width < 8)
1274 cfg->host_caps &= ~MMC_MODE_8BIT;
1275 if (priv->bus_width < 4)
1276 cfg->host_caps &= ~MMC_MODE_4BIT;
1277 }
1278
1279 if (caps & ESDHC_HOSTCAPBLT_HSS)
1280 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1281
1282#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1283 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1284 cfg->host_caps &= ~MMC_MODE_8BIT;
1285#endif
1286
1287 cfg->host_caps |= priv->caps;
1288
1289 cfg->f_min = 400000;
1290 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1291
1292 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1293
Haibo Chen920f5d02020-09-30 15:52:23 +08001294 esdhc_write32(&regs->dllctrl, 0);
Yangbo Lu982f4252019-06-21 11:42:27 +08001295 if (priv->flags & ESDHC_FLAG_USDHC) {
1296 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chen920f5d02020-09-30 15:52:23 +08001297 u32 val = esdhc_read32(&regs->tuning_ctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +08001298
1299 val |= ESDHC_STD_TUNING_EN;
1300 val &= ~ESDHC_TUNING_START_TAP_MASK;
1301 val |= priv->tuning_start_tap;
1302 val &= ~ESDHC_TUNING_STEP_MASK;
1303 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
Haibo Chen43162c32020-06-22 19:38:04 +08001304
1305 /* Disable the CMD CRC check for tuning, if not, need to
1306 * add some delay after every tuning command, because
1307 * hardware standard tuning logic will directly go to next
1308 * step once it detect the CMD CRC error, will not wait for
1309 * the card side to finally send out the tuning data, trigger
1310 * the buffer read ready interrupt immediately. If usdhc send
1311 * the next tuning command some eMMC card will stuck, can't
1312 * response, block the tuning procedure or the first command
1313 * after the whole tuning procedure always can't get any response.
1314 */
1315 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
Haibo Chen920f5d02020-09-30 15:52:23 +08001316 esdhc_write32(&regs->tuning_ctrl, val);
Yangbo Lu982f4252019-06-21 11:42:27 +08001317 }
1318 }
1319
1320 return 0;
1321}
1322
1323#if !CONFIG_IS_ENABLED(DM_MMC)
1324static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1325 struct fsl_esdhc_priv *priv)
1326{
1327 if (!cfg || !priv)
1328 return -EINVAL;
1329
1330 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1331 priv->bus_width = cfg->max_bus_width;
1332 priv->sdhc_clk = cfg->sdhc_clk;
1333 priv->wp_enable = cfg->wp_enable;
1334 priv->vs18_enable = cfg->vs18_enable;
1335
1336 return 0;
1337};
1338
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001339int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
Yangbo Lu982f4252019-06-21 11:42:27 +08001340{
1341 struct fsl_esdhc_plat *plat;
1342 struct fsl_esdhc_priv *priv;
1343 struct mmc *mmc;
1344 int ret;
1345
1346 if (!cfg)
1347 return -EINVAL;
1348
1349 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1350 if (!priv)
1351 return -ENOMEM;
1352 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1353 if (!plat) {
1354 free(priv);
1355 return -ENOMEM;
1356 }
1357
1358 ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1359 if (ret) {
1360 debug("%s xlate failure\n", __func__);
1361 free(plat);
1362 free(priv);
1363 return ret;
1364 }
1365
1366 ret = fsl_esdhc_init(priv, plat);
1367 if (ret) {
1368 debug("%s init failure\n", __func__);
1369 free(plat);
1370 free(priv);
1371 return ret;
1372 }
1373
1374 mmc = mmc_create(&plat->cfg, priv);
1375 if (!mmc)
1376 return -EIO;
1377
1378 priv->mmc = mmc;
1379
1380 return 0;
1381}
1382
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001383int fsl_esdhc_mmc_init(struct bd_info *bis)
Yangbo Lu982f4252019-06-21 11:42:27 +08001384{
1385 struct fsl_esdhc_cfg *cfg;
1386
1387 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1388 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1389 cfg->sdhc_clk = gd->arch.sdhc_clk;
1390 return fsl_esdhc_initialize(bis, cfg);
1391}
1392#endif
1393
Yangbo Lu982f4252019-06-21 11:42:27 +08001394#ifdef CONFIG_OF_LIBFDT
1395__weak int esdhc_status_fixup(void *blob, const char *compat)
1396{
1397#ifdef CONFIG_FSL_ESDHC_PIN_MUX
1398 if (!hwconfig("esdhc")) {
1399 do_fixup_by_compat(blob, compat, "status", "disabled",
1400 sizeof("disabled"), 1);
1401 return 1;
1402 }
1403#endif
1404 return 0;
1405}
1406
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001407void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
Yangbo Lu982f4252019-06-21 11:42:27 +08001408{
1409 const char *compat = "fsl,esdhc";
1410
1411 if (esdhc_status_fixup(blob, compat))
1412 return;
1413
Yangbo Lu982f4252019-06-21 11:42:27 +08001414 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1415 gd->arch.sdhc_clk, 1);
Yangbo Lu982f4252019-06-21 11:42:27 +08001416}
1417#endif
1418
1419#if CONFIG_IS_ENABLED(DM_MMC)
Yangbo Lu982f4252019-06-21 11:42:27 +08001420#include <asm/arch/clock.h>
Yangbo Lu982f4252019-06-21 11:42:27 +08001421__weak void init_clk_usdhc(u32 index)
1422{
1423}
1424
Simon Glassaad29ae2020-12-03 16:55:21 -07001425static int fsl_esdhc_of_to_plat(struct udevice *dev)
Yangbo Lu982f4252019-06-21 11:42:27 +08001426{
Walter Lozano8aff6732020-07-29 12:31:17 -03001427#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Yangbo Lu982f4252019-06-21 11:42:27 +08001428 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001429#if CONFIG_IS_ENABLED(DM_REGULATOR)
1430 struct udevice *vqmmc_dev;
Walter Lozano8aff6732020-07-29 12:31:17 -03001431 int ret;
Yangbo Lu982f4252019-06-21 11:42:27 +08001432#endif
Walter Lozano8aff6732020-07-29 12:31:17 -03001433 const void *fdt = gd->fdt_blob;
1434 int node = dev_of_offset(dev);
1435
Yangbo Lu982f4252019-06-21 11:42:27 +08001436 fdt_addr_t addr;
1437 unsigned int val;
Yangbo Lu982f4252019-06-21 11:42:27 +08001438
1439 addr = dev_read_addr(dev);
1440 if (addr == FDT_ADDR_T_NONE)
1441 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +08001442 priv->esdhc_regs = (struct fsl_esdhc *)addr;
Yangbo Lu982f4252019-06-21 11:42:27 +08001443 priv->dev = dev;
1444 priv->mode = -1;
Yangbo Lu982f4252019-06-21 11:42:27 +08001445
1446 val = dev_read_u32_default(dev, "bus-width", -1);
1447 if (val == 8)
1448 priv->bus_width = 8;
1449 else if (val == 4)
1450 priv->bus_width = 4;
1451 else
1452 priv->bus_width = 1;
1453
1454 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1455 priv->tuning_step = val;
1456 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1457 ESDHC_TUNING_START_TAP_DEFAULT);
1458 priv->tuning_start_tap = val;
1459 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1460 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1461 priv->strobe_dll_delay_target = val;
1462
Fabio Estevam7e3d8a92020-01-06 20:11:27 -03001463 if (dev_read_bool(dev, "broken-cd"))
1464 priv->broken_cd = 1;
1465
Yangbo Lu982f4252019-06-21 11:42:27 +08001466 if (dev_read_bool(dev, "non-removable")) {
1467 priv->non_removable = 1;
1468 } else {
1469 priv->non_removable = 0;
Simon Glassfa4689a2019-12-06 21:41:35 -07001470#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lu982f4252019-06-21 11:42:27 +08001471 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1472 GPIOD_IS_IN);
1473#endif
1474 }
1475
1476 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1477 priv->wp_enable = 1;
1478 } else {
1479 priv->wp_enable = 0;
Simon Glassfa4689a2019-12-06 21:41:35 -07001480#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lu982f4252019-06-21 11:42:27 +08001481 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1482 GPIOD_IS_IN);
1483#endif
1484 }
1485
1486 priv->vs18_enable = 0;
1487
1488#if CONFIG_IS_ENABLED(DM_REGULATOR)
1489 /*
1490 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1491 * otherwise, emmc will work abnormally.
1492 */
1493 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1494 if (ret) {
1495 dev_dbg(dev, "no vqmmc-supply\n");
1496 } else {
Marek Vasut34e67f92020-05-22 18:19:08 +02001497 priv->vqmmc_dev = vqmmc_dev;
Yangbo Lu982f4252019-06-21 11:42:27 +08001498 ret = regulator_set_enable(vqmmc_dev, true);
1499 if (ret) {
1500 dev_err(dev, "fail to enable vqmmc-supply\n");
1501 return ret;
1502 }
1503
1504 if (regulator_get_value(vqmmc_dev) == 1800000)
1505 priv->vs18_enable = 1;
1506 }
1507#endif
Walter Lozano8aff6732020-07-29 12:31:17 -03001508#endif
1509 return 0;
1510}
1511
1512static int fsl_esdhc_probe(struct udevice *dev)
1513{
1514 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -07001515 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Walter Lozano8aff6732020-07-29 12:31:17 -03001516 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1517 struct esdhc_soc_data *data =
1518 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1519 struct mmc *mmc;
1520#if !CONFIG_IS_ENABLED(BLK)
1521 struct blk_desc *bdesc;
1522#endif
1523 int ret;
1524
1525#if CONFIG_IS_ENABLED(OF_PLATDATA)
1526 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
1527 unsigned int val;
1528
1529 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
1530 val = plat->dtplat.bus_width;
1531 if (val == 8)
1532 priv->bus_width = 8;
1533 else if (val == 4)
1534 priv->bus_width = 4;
1535 else
1536 priv->bus_width = 1;
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001537
1538 if (dtplat->non_removable)
1539 priv->non_removable = 1;
1540 else
1541 priv->non_removable = 0;
1542
1543 if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
1544 struct udevice *gpiodev;
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001545
Simon Glass0000e0d2021-03-15 17:25:28 +13001546 ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev);
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001547 if (ret)
1548 return ret;
1549
1550 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1551 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1552 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1553
1554 if (ret)
1555 return ret;
1556 }
Walter Lozano8aff6732020-07-29 12:31:17 -03001557#endif
1558
1559 if (data)
1560 priv->flags = data->flags;
Yangbo Lu982f4252019-06-21 11:42:27 +08001561
Yangbo Lu982f4252019-06-21 11:42:27 +08001562 /*
1563 * TODO:
1564 * Because lack of clk driver, if SDHC clk is not enabled,
1565 * need to enable it first before this driver is invoked.
1566 *
1567 * we use MXC_ESDHC_CLK to get clk freq.
1568 * If one would like to make this function work,
1569 * the aliases should be provided in dts as this:
1570 *
1571 * aliases {
1572 * mmc0 = &usdhc1;
1573 * mmc1 = &usdhc2;
1574 * mmc2 = &usdhc3;
1575 * mmc3 = &usdhc4;
1576 * };
1577 * Then if your board only supports mmc2 and mmc3, but we can
1578 * correctly get the seq as 2 and 3, then let mxc_get_clock
1579 * work as expected.
1580 */
1581
Simon Glass75e534b2020-12-16 21:20:07 -07001582 init_clk_usdhc(dev_seq(dev));
Yangbo Lu982f4252019-06-21 11:42:27 +08001583
Giulio Benettidbdbc632020-01-10 15:51:45 +01001584#if CONFIG_IS_ENABLED(CLK)
1585 /* Assigned clock already set clock */
1586 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1587 if (ret) {
1588 printf("Failed to get per_clk\n");
1589 return ret;
1590 }
1591 ret = clk_enable(&priv->per_clk);
1592 if (ret) {
1593 printf("Failed to enable per_clk\n");
1594 return ret;
1595 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001596
Giulio Benettidbdbc632020-01-10 15:51:45 +01001597 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1598#else
Simon Glass75e534b2020-12-16 21:20:07 -07001599 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
Giulio Benettidbdbc632020-01-10 15:51:45 +01001600 if (priv->sdhc_clk <= 0) {
1601 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1602 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +08001603 }
Giulio Benettidbdbc632020-01-10 15:51:45 +01001604#endif
Yangbo Lu982f4252019-06-21 11:42:27 +08001605
1606 ret = fsl_esdhc_init(priv, plat);
1607 if (ret) {
1608 dev_err(dev, "fsl_esdhc_init failure\n");
1609 return ret;
1610 }
1611
Walter Lozano8aff6732020-07-29 12:31:17 -03001612#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Peng Fan3766a482019-07-10 09:35:24 +00001613 ret = mmc_of_parse(dev, &plat->cfg);
1614 if (ret)
1615 return ret;
Walter Lozano8aff6732020-07-29 12:31:17 -03001616#endif
Peng Fan3766a482019-07-10 09:35:24 +00001617
Yangbo Lu982f4252019-06-21 11:42:27 +08001618 mmc = &plat->mmc;
1619 mmc->cfg = &plat->cfg;
1620 mmc->dev = dev;
1621#if !CONFIG_IS_ENABLED(BLK)
1622 mmc->priv = priv;
1623
1624 /* Setup dsr related values */
1625 mmc->dsr_imp = 0;
1626 mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1627 /* Setup the universal parts of the block interface just once */
1628 bdesc = mmc_get_blk_desc(mmc);
1629 bdesc->if_type = IF_TYPE_MMC;
1630 bdesc->removable = 1;
1631 bdesc->devnum = mmc_get_next_devnum();
1632 bdesc->block_read = mmc_bread;
1633 bdesc->block_write = mmc_bwrite;
1634 bdesc->block_erase = mmc_berase;
1635
1636 /* setup initial part type */
1637 bdesc->part_type = mmc->cfg->part_type;
1638 mmc_list_add(mmc);
1639#endif
1640
1641 upriv->mmc = mmc;
1642
1643 return esdhc_init_common(priv, mmc);
1644}
1645
1646#if CONFIG_IS_ENABLED(DM_MMC)
1647static int fsl_esdhc_get_cd(struct udevice *dev)
1648{
1649 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1650
1651 return esdhc_getcd_common(priv);
1652}
1653
1654static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1655 struct mmc_data *data)
1656{
Simon Glassfa20e932020-12-03 16:55:20 -07001657 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001658 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1659
1660 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1661}
1662
1663static int fsl_esdhc_set_ios(struct udevice *dev)
1664{
Simon Glassfa20e932020-12-03 16:55:20 -07001665 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001666 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1667
1668 return esdhc_set_ios_common(priv, &plat->mmc);
1669}
1670
Peng Fan69b9d3a2019-07-10 09:35:26 +00001671#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1672static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1673{
1674 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1675 struct fsl_esdhc *regs = priv->esdhc_regs;
1676 u32 m;
1677
Haibo Chen920f5d02020-09-30 15:52:23 +08001678 m = esdhc_read32(&regs->mixctrl);
Peng Fan69b9d3a2019-07-10 09:35:26 +00001679 m |= MIX_CTRL_HS400_ES;
Haibo Chen920f5d02020-09-30 15:52:23 +08001680 esdhc_write32(&regs->mixctrl, m);
Peng Fan69b9d3a2019-07-10 09:35:26 +00001681
1682 return 0;
1683}
1684#endif
1685
Haibo Chencb78f212020-11-05 14:57:13 +08001686static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1687 int timeout_us)
1688{
1689 int ret;
1690 u32 tmp;
1691 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1692 struct fsl_esdhc *regs = priv->esdhc_regs;
1693
1694 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp,
1695 !!(tmp & PRSSTAT_DAT0) == !!state,
1696 timeout_us);
1697 return ret;
1698}
1699
Yangbo Lu982f4252019-06-21 11:42:27 +08001700static const struct dm_mmc_ops fsl_esdhc_ops = {
1701 .get_cd = fsl_esdhc_get_cd,
1702 .send_cmd = fsl_esdhc_send_cmd,
1703 .set_ios = fsl_esdhc_set_ios,
1704#ifdef MMC_SUPPORTS_TUNING
1705 .execute_tuning = fsl_esdhc_execute_tuning,
1706#endif
Peng Fan69b9d3a2019-07-10 09:35:26 +00001707#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1708 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1709#endif
Haibo Chencb78f212020-11-05 14:57:13 +08001710 .wait_dat0 = fsl_esdhc_wait_dat0,
Yangbo Lu982f4252019-06-21 11:42:27 +08001711};
1712#endif
1713
1714static struct esdhc_soc_data usdhc_imx7d_data = {
1715 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1716 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1717 | ESDHC_FLAG_HS400,
Yangbo Lu982f4252019-06-21 11:42:27 +08001718};
1719
Peng Fan457fe962019-07-10 09:35:28 +00001720static struct esdhc_soc_data usdhc_imx8qm_data = {
1721 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1722 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1723 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1724};
1725
Yangbo Lu982f4252019-06-21 11:42:27 +08001726static const struct udevice_id fsl_esdhc_ids[] = {
Fabio Estevameaf8ccc2021-02-15 08:58:15 -03001727 { .compatible = "fsl,imx51-esdhc", },
Yangbo Lu982f4252019-06-21 11:42:27 +08001728 { .compatible = "fsl,imx53-esdhc", },
1729 { .compatible = "fsl,imx6ul-usdhc", },
1730 { .compatible = "fsl,imx6sx-usdhc", },
1731 { .compatible = "fsl,imx6sl-usdhc", },
1732 { .compatible = "fsl,imx6q-usdhc", },
1733 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1734 { .compatible = "fsl,imx7ulp-usdhc", },
Peng Fan457fe962019-07-10 09:35:28 +00001735 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Peng Fand7689fa2019-11-04 17:31:17 +08001736 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1737 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1738 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Giulio Benetti65b5ec12020-01-10 15:51:46 +01001739 { .compatible = "fsl,imxrt-usdhc", },
Yangbo Lu982f4252019-06-21 11:42:27 +08001740 { .compatible = "fsl,esdhc", },
1741 { /* sentinel */ }
1742};
1743
1744#if CONFIG_IS_ENABLED(BLK)
1745static int fsl_esdhc_bind(struct udevice *dev)
1746{
Simon Glassfa20e932020-12-03 16:55:20 -07001747 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001748
1749 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1750}
1751#endif
1752
1753U_BOOT_DRIVER(fsl_esdhc) = {
Walter Lozano904b0be2020-07-29 12:31:16 -03001754 .name = "fsl_esdhc",
Yangbo Lu982f4252019-06-21 11:42:27 +08001755 .id = UCLASS_MMC,
1756 .of_match = fsl_esdhc_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -07001757 .of_to_plat = fsl_esdhc_of_to_plat,
Yangbo Lu982f4252019-06-21 11:42:27 +08001758 .ops = &fsl_esdhc_ops,
1759#if CONFIG_IS_ENABLED(BLK)
1760 .bind = fsl_esdhc_bind,
1761#endif
1762 .probe = fsl_esdhc_probe,
Simon Glass71fa5b42020-12-03 16:55:18 -07001763 .plat_auto = sizeof(struct fsl_esdhc_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -07001764 .priv_auto = sizeof(struct fsl_esdhc_priv),
Yangbo Lu982f4252019-06-21 11:42:27 +08001765};
Walter Lozano8aff6732020-07-29 12:31:17 -03001766
Simon Glassdf65db82020-12-28 20:34:57 -07001767DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
Yangbo Lu982f4252019-06-21 11:42:27 +08001768#endif