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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkaffae2b2002-08-17 09:36:01 +00002/*
3 * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
4 *
wdenkc0bc2e12004-02-09 23:12:24 +00005 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
6 * Stephan Linz <linz@li-pro.net>
wdenkaffae2b2002-08-17 09:36:01 +00007 */
8
9/*
wdenkc0bc2e12004-02-09 23:12:24 +000010 * Date & Time support for DS1306 RTC using SPI:
11 *
12 * - SXNI855T: it uses its own soft SPI here in this file
13 * - all other: use the external spi_xfer() function
14 * (see include/spi.h)
wdenkaffae2b2002-08-17 09:36:01 +000015 */
16
17#include <common.h>
18#include <command.h>
19#include <rtc.h>
wdenkc0bc2e12004-02-09 23:12:24 +000020#include <spi.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
wdenkaffae2b2002-08-17 09:36:01 +000022
wdenkc0bc2e12004-02-09 23:12:24 +000023#define RTC_SECONDS 0x00
24#define RTC_MINUTES 0x01
25#define RTC_HOURS 0x02
26#define RTC_DAY_OF_WEEK 0x03
27#define RTC_DATE_OF_MONTH 0x04
28#define RTC_MONTH 0x05
29#define RTC_YEAR 0x06
30
31#define RTC_SECONDS_ALARM0 0x07
32#define RTC_MINUTES_ALARM0 0x08
33#define RTC_HOURS_ALARM0 0x09
34#define RTC_DAY_OF_WEEK_ALARM0 0x0a
35
36#define RTC_SECONDS_ALARM1 0x0b
37#define RTC_MINUTES_ALARM1 0x0c
38#define RTC_HOURS_ALARM1 0x0d
39#define RTC_DAY_OF_WEEK_ALARM1 0x0e
40
41#define RTC_CONTROL 0x0f
42#define RTC_STATUS 0x10
43#define RTC_TRICKLE_CHARGER 0x11
44
45#define RTC_USER_RAM_BASE 0x20
46
wdenkc0bc2e12004-02-09 23:12:24 +000047/* ************************************************************************* */
48#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
49
50static void soft_spi_send (unsigned char n);
51static unsigned char soft_spi_read (void);
52static void init_spi (void);
wdenkaffae2b2002-08-17 09:36:01 +000053
54/*-----------------------------------------------------------------------
55 * Definitions
56 */
57
58#define PB_SPISCK 0x00000002 /* PB 30 */
59#define PB_SPIMOSI 0x00000004 /* PB 29 */
60#define PB_SPIMISO 0x00000008 /* PB 28 */
61#define PB_SPI_CE 0x00010000 /* PB 15 */
62
63/* ------------------------------------------------------------------------- */
64
65/* read clock time from DS1306 and return it in *tmp */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +030066int rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000067{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc0bc2e12004-02-09 23:12:24 +000069 unsigned char spi_byte; /* Data Byte */
wdenkaffae2b2002-08-17 09:36:01 +000070
wdenkc0bc2e12004-02-09 23:12:24 +000071 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +000072
wdenkc0bc2e12004-02-09 23:12:24 +000073 /* Now we can enable the DS1306 RTC */
74 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
Simon Glass0db4b942020-05-10 11:40:10 -060075 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +000076
wdenkc0bc2e12004-02-09 23:12:24 +000077 /* Shift out the address (0) of the time in the Clock Chip */
78 soft_spi_send (0);
wdenkaffae2b2002-08-17 09:36:01 +000079
wdenkc0bc2e12004-02-09 23:12:24 +000080 /* Put the clock readings into the rtc_time structure */
81 tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
82 tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
wdenkaffae2b2002-08-17 09:36:01 +000083
wdenkc0bc2e12004-02-09 23:12:24 +000084 /* Hours are trickier */
85 spi_byte = soft_spi_read (); /* Read Hours into temporary value */
86 if (spi_byte & 0x40) {
87 /* 12 hour mode bit is set (time is in 1-12 format) */
88 if (spi_byte & 0x20) {
89 /* since PM we add 11 to get 0-23 for hours */
90 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
91 } else {
92 /* since AM we subtract 1 to get 0-23 for hours */
93 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
94 }
95 } else {
96 /* Otherwise, 0-23 hour format */
97 tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
wdenkaffae2b2002-08-17 09:36:01 +000098 }
wdenkaffae2b2002-08-17 09:36:01 +000099
wdenkc0bc2e12004-02-09 23:12:24 +0000100 soft_spi_read (); /* Read and discard Day of week */
101 tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
102 tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
wdenkaffae2b2002-08-17 09:36:01 +0000103
wdenkc0bc2e12004-02-09 23:12:24 +0000104 /* Read Year and convert to this century */
105 tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
wdenkaffae2b2002-08-17 09:36:01 +0000106
wdenkc0bc2e12004-02-09 23:12:24 +0000107 /* Now we can disable the DS1306 RTC */
108 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
Simon Glass0db4b942020-05-10 11:40:10 -0600109 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000110
Simon Glass2d937bb2015-04-20 12:37:17 -0600111 rtc_calc_weekday(tmp); /* Determine the day of week */
wdenkaffae2b2002-08-17 09:36:01 +0000112
wdenkc0bc2e12004-02-09 23:12:24 +0000113 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
114 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
115 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300116
117 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000118}
119
120/* ------------------------------------------------------------------------- */
121
122/* set clock time in DS1306 RTC and in MPC8xx RTC */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200123int rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000124{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000126
wdenkc0bc2e12004-02-09 23:12:24 +0000127 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000128
wdenkc0bc2e12004-02-09 23:12:24 +0000129 /* Now we can enable the DS1306 RTC */
130 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
Simon Glass0db4b942020-05-10 11:40:10 -0600131 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000132
wdenkc0bc2e12004-02-09 23:12:24 +0000133 /* First disable write protect in the clock chip control register */
134 soft_spi_send (0x8F); /* send address of the control register */
135 soft_spi_send (0x00); /* send control register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000136
wdenkc0bc2e12004-02-09 23:12:24 +0000137 /* Now disable the DS1306 to terminate the write */
138 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
Simon Glass0db4b942020-05-10 11:40:10 -0600139 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000140
wdenkc0bc2e12004-02-09 23:12:24 +0000141 /* Now enable the DS1306 to initiate a new write */
142 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
Simon Glass0db4b942020-05-10 11:40:10 -0600143 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000144
wdenkc0bc2e12004-02-09 23:12:24 +0000145 /* Next, send the address of the clock time write registers */
146 soft_spi_send (0x80); /* send address of the first time register */
wdenkaffae2b2002-08-17 09:36:01 +0000147
wdenkc0bc2e12004-02-09 23:12:24 +0000148 /* Use Burst Mode to send all of the time data to the clock */
149 bin2bcd (tmp->tm_sec);
150 soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
151 soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
152 soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
153 soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
154 soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
155 soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
156 soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
wdenkaffae2b2002-08-17 09:36:01 +0000157
wdenkc0bc2e12004-02-09 23:12:24 +0000158 /* Now we can disable the Clock chip to terminate the burst write */
159 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
Simon Glass0db4b942020-05-10 11:40:10 -0600160 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000161
wdenkc0bc2e12004-02-09 23:12:24 +0000162 /* Now we can enable the Clock chip to initiate a new write */
163 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
Simon Glass0db4b942020-05-10 11:40:10 -0600164 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000165
wdenkc0bc2e12004-02-09 23:12:24 +0000166 /* First we Enable write protect in the clock chip control register */
167 soft_spi_send (0x8F); /* send address of the control register */
168 soft_spi_send (0x40); /* send out Control Register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000169
wdenkc0bc2e12004-02-09 23:12:24 +0000170 /* Now disable the DS1306 */
171 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
Simon Glass0db4b942020-05-10 11:40:10 -0600172 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000173
wdenkc0bc2e12004-02-09 23:12:24 +0000174 /* Set standard MPC8xx clock to the same time so Linux will
175 * see the time even if it doesn't have a DS1306 clock driver.
176 * This helps with experimenting with standard kernels.
177 */
178 {
179 ulong tim;
wdenkaffae2b2002-08-17 09:36:01 +0000180
Simon Glass4283e842015-04-20 12:37:19 -0600181 tim = rtc_mktime(tmp);
wdenkaffae2b2002-08-17 09:36:01 +0000182
wdenkc0bc2e12004-02-09 23:12:24 +0000183 immap->im_sitk.sitk_rtck = KAPWR_KEY;
184 immap->im_sit.sit_rtc = tim;
185 }
wdenkaffae2b2002-08-17 09:36:01 +0000186
wdenkc0bc2e12004-02-09 23:12:24 +0000187 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
188 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
189 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200190
191 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000192}
193
194/* ------------------------------------------------------------------------- */
195
wdenkc0bc2e12004-02-09 23:12:24 +0000196/* Initialize Port B for software SPI */
197static void init_spi (void)
wdenkaffae2b2002-08-17 09:36:01 +0000198{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc0bc2e12004-02-09 23:12:24 +0000200
201 /* Force output pins to begin at logic 0 */
202 immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
203
204 /* Set these 3 signals as outputs */
205 immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
206
207 immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
Simon Glass0db4b942020-05-10 11:40:10 -0600208 udelay(10);
wdenkaffae2b2002-08-17 09:36:01 +0000209}
210
211/* ------------------------------------------------------------------------- */
212
wdenkc0bc2e12004-02-09 23:12:24 +0000213/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
214static void soft_spi_send (unsigned char n)
wdenkaffae2b2002-08-17 09:36:01 +0000215{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc0bc2e12004-02-09 23:12:24 +0000217 unsigned char bitpos; /* bit position to receive */
218 unsigned char i; /* Loop Control */
219
220 /* bit position to send, start with most significant bit */
221 bitpos = 0x80;
222
223 /* Send 8 bits to software SPI */
224 for (i = 0; i < 8; i++) { /* Loop for 8 bits */
225 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
226
227 if (n & bitpos)
228 immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
229 else
230 immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
Simon Glass0db4b942020-05-10 11:40:10 -0600231 udelay(10);
wdenkc0bc2e12004-02-09 23:12:24 +0000232
233 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
Simon Glass0db4b942020-05-10 11:40:10 -0600234 udelay(10);
wdenkc0bc2e12004-02-09 23:12:24 +0000235
236 bitpos >>= 1; /* Shift for next bit position */
237 }
wdenkaffae2b2002-08-17 09:36:01 +0000238}
239
240/* ------------------------------------------------------------------------- */
241
wdenkc0bc2e12004-02-09 23:12:24 +0000242/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
243static unsigned char soft_spi_read (void)
wdenkaffae2b2002-08-17 09:36:01 +0000244{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200245 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc0bc2e12004-02-09 23:12:24 +0000246
247 unsigned char spi_byte = 0; /* Return value, assume success */
248 unsigned char bitpos; /* bit position to receive */
249 unsigned char i; /* Loop Control */
250
251 /* bit position to receive, start with most significant bit */
252 bitpos = 0x80;
253
254 /* Read 8 bits here */
255 for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
256 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
Simon Glass0db4b942020-05-10 11:40:10 -0600257 udelay(10);
wdenkc0bc2e12004-02-09 23:12:24 +0000258 if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
259 spi_byte |= bitpos; /* Set data accordingly */
260 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
Simon Glass0db4b942020-05-10 11:40:10 -0600261 udelay(10);
wdenkc0bc2e12004-02-09 23:12:24 +0000262 bitpos >>= 1; /* Shift for next bit position */
263 }
264
265 return spi_byte; /* Return the byte read */
wdenkaffae2b2002-08-17 09:36:01 +0000266}
267
268/* ------------------------------------------------------------------------- */
269
wdenkc0bc2e12004-02-09 23:12:24 +0000270void rtc_reset (void)
271{
272 return; /* nothing to do */
273}
wdenkaffae2b2002-08-17 09:36:01 +0000274
wdenkc0bc2e12004-02-09 23:12:24 +0000275#else /* not CONFIG_SXNI855T */
276/* ************************************************************************* */
wdenkaffae2b2002-08-17 09:36:01 +0000277
wdenkef893942004-02-23 16:11:30 +0000278static unsigned char rtc_read (unsigned char reg);
279static void rtc_write (unsigned char reg, unsigned char val);
280
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200281static struct spi_slave *slave;
282
wdenkc0bc2e12004-02-09 23:12:24 +0000283/* read clock time from DS1306 and return it in *tmp */
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300284int rtc_get (struct rtc_time *tmp)
wdenkc0bc2e12004-02-09 23:12:24 +0000285{
286 unsigned char sec, min, hour, mday, wday, mon, year;
287
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200288 /*
289 * Assuming Vcc = 2.0V (lowest speed)
290 *
291 * REVISIT: If we add an rtc_init() function we can do this
292 * step just once.
293 */
294 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200296 SPI_MODE_3 | SPI_CS_HIGH);
297 if (!slave)
298 return;
299 }
300
301 if (spi_claim_bus(slave))
302 return;
303
wdenkc0bc2e12004-02-09 23:12:24 +0000304 sec = rtc_read (RTC_SECONDS);
305 min = rtc_read (RTC_MINUTES);
306 hour = rtc_read (RTC_HOURS);
307 mday = rtc_read (RTC_DATE_OF_MONTH);
308 wday = rtc_read (RTC_DAY_OF_WEEK);
309 mon = rtc_read (RTC_MONTH);
310 year = rtc_read (RTC_YEAR);
311
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200312 spi_release_bus(slave);
313
wdenkc0bc2e12004-02-09 23:12:24 +0000314 debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
315 "hr: %02x min: %02x sec: %02x\n",
316 year, mon, mday, wday, hour, min, sec);
317 debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
318 rtc_read (RTC_DAY_OF_WEEK_ALARM0),
319 rtc_read (RTC_HOURS_ALARM0),
320 rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
321 debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
322 rtc_read (RTC_DAY_OF_WEEK_ALARM1),
323 rtc_read (RTC_HOURS_ALARM1),
324 rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
325
326 tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
327 tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
328
329 /* convert Hours */
330 tmp->tm_hour = (hour & 0x40)
331 ? ((hour & 0x20) /* 12 hour mode */
332 ? bcd2bin (hour & 0x1F) + 11 /* PM */
333 : bcd2bin (hour & 0x1F) - 1 /* AM */
334 )
335 : bcd2bin (hour & 0x3F); /* 24 hour mode */
336
337 tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
338 tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
339 tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
340 tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
341 tmp->tm_yday = 0;
342 tmp->tm_isdst = 0;
343
344 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
345 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
346 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonov9bacd942008-03-20 17:56:04 +0300347
348 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000349}
350
351/* ------------------------------------------------------------------------- */
352
wdenkc0bc2e12004-02-09 23:12:24 +0000353/* set clock time from *tmp in DS1306 RTC */
Jean-Christophe PLAGNIOL-VILLARD97a2e102008-09-01 23:06:23 +0200354int rtc_set (struct rtc_time *tmp)
wdenkc0bc2e12004-02-09 23:12:24 +0000355{
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200356 /* Assuming Vcc = 2.0V (lowest speed) */
357 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200358 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200359 SPI_MODE_3 | SPI_CS_HIGH);
360 if (!slave)
361 return;
362 }
363
364 if (spi_claim_bus(slave))
365 return;
366
wdenkc0bc2e12004-02-09 23:12:24 +0000367 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
368 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
369 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
370
wdenkc0bc2e12004-02-09 23:12:24 +0000371 rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
Wolfgang Denk21d05832006-05-03 01:04:58 +0200372 rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
373 rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
374 rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
375 rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
376 rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
377 rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200378
379 spi_release_bus(slave);
wdenkc0bc2e12004-02-09 23:12:24 +0000380}
381
382/* ------------------------------------------------------------------------- */
383
384/* reset the DS1306 */
385void rtc_reset (void)
wdenkaffae2b2002-08-17 09:36:01 +0000386{
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200387 /* Assuming Vcc = 2.0V (lowest speed) */
388 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200389 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200390 SPI_MODE_3 | SPI_CS_HIGH);
391 if (!slave)
392 return;
393 }
394
395 if (spi_claim_bus(slave))
396 return;
397
wdenkc0bc2e12004-02-09 23:12:24 +0000398 /* clear the control register */
399 rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
400 rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
wdenkaffae2b2002-08-17 09:36:01 +0000401
wdenkc0bc2e12004-02-09 23:12:24 +0000402 /* reset all alarms */
403 rtc_write (RTC_SECONDS_ALARM0, 0x00);
404 rtc_write (RTC_SECONDS_ALARM1, 0x00);
405 rtc_write (RTC_MINUTES_ALARM0, 0x00);
406 rtc_write (RTC_MINUTES_ALARM1, 0x00);
407 rtc_write (RTC_HOURS_ALARM0, 0x00);
408 rtc_write (RTC_HOURS_ALARM1, 0x00);
409 rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
410 rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200411
412 spi_release_bus(slave);
wdenkc0bc2e12004-02-09 23:12:24 +0000413}
wdenkaffae2b2002-08-17 09:36:01 +0000414
wdenkc0bc2e12004-02-09 23:12:24 +0000415/* ------------------------------------------------------------------------- */
wdenkaffae2b2002-08-17 09:36:01 +0000416
wdenkc0bc2e12004-02-09 23:12:24 +0000417static unsigned char rtc_read (unsigned char reg)
418{
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200419 int ret;
wdenkaffae2b2002-08-17 09:36:01 +0000420
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200421 ret = spi_w8r8(slave, reg);
422 return ret < 0 ? 0 : ret;
wdenkaffae2b2002-08-17 09:36:01 +0000423}
424
425/* ------------------------------------------------------------------------- */
426
wdenkc0bc2e12004-02-09 23:12:24 +0000427static void rtc_write (unsigned char reg, unsigned char val)
wdenkaffae2b2002-08-17 09:36:01 +0000428{
wdenkc0bc2e12004-02-09 23:12:24 +0000429 unsigned char dout[2]; /* SPI Output Data Bytes */
430 unsigned char din[2]; /* SPI Input Data Bytes */
wdenkaffae2b2002-08-17 09:36:01 +0000431
wdenkc0bc2e12004-02-09 23:12:24 +0000432 dout[0] = 0x80 | reg;
433 dout[1] = val;
wdenkaffae2b2002-08-17 09:36:01 +0000434
Haavard Skinnemoend74084a2008-05-16 11:10:31 +0200435 spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
wdenkc0bc2e12004-02-09 23:12:24 +0000436}
437
438#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */