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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
3 *
wdenkc0bc2e12004-02-09 23:12:24 +00004 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
5 * Stephan Linz <linz@li-pro.net>
6 *
wdenkaffae2b2002-08-17 09:36:01 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
wdenkc0bc2e12004-02-09 23:12:24 +000027 * Date & Time support for DS1306 RTC using SPI:
28 *
29 * - SXNI855T: it uses its own soft SPI here in this file
30 * - all other: use the external spi_xfer() function
31 * (see include/spi.h)
wdenkaffae2b2002-08-17 09:36:01 +000032 */
33
34#include <common.h>
35#include <command.h>
36#include <rtc.h>
wdenkc0bc2e12004-02-09 23:12:24 +000037#include <spi.h>
wdenkaffae2b2002-08-17 09:36:01 +000038
39#if defined(CONFIG_RTC_DS1306) && (CONFIG_COMMANDS & CFG_CMD_DATE)
40
wdenkc0bc2e12004-02-09 23:12:24 +000041#define RTC_SECONDS 0x00
42#define RTC_MINUTES 0x01
43#define RTC_HOURS 0x02
44#define RTC_DAY_OF_WEEK 0x03
45#define RTC_DATE_OF_MONTH 0x04
46#define RTC_MONTH 0x05
47#define RTC_YEAR 0x06
48
49#define RTC_SECONDS_ALARM0 0x07
50#define RTC_MINUTES_ALARM0 0x08
51#define RTC_HOURS_ALARM0 0x09
52#define RTC_DAY_OF_WEEK_ALARM0 0x0a
53
54#define RTC_SECONDS_ALARM1 0x0b
55#define RTC_MINUTES_ALARM1 0x0c
56#define RTC_HOURS_ALARM1 0x0d
57#define RTC_DAY_OF_WEEK_ALARM1 0x0e
58
59#define RTC_CONTROL 0x0f
60#define RTC_STATUS 0x10
61#define RTC_TRICKLE_CHARGER 0x11
62
63#define RTC_USER_RAM_BASE 0x20
64
65/*
66 * External table of chip select functions (see the appropriate board
67 * support for the actual definition of the table).
68 */
69extern spi_chipsel_type spi_chipsel[];
70extern int spi_chipsel_cnt;
71
72static unsigned int bin2bcd (unsigned int n);
73static unsigned char bcd2bin (unsigned char c);
74static unsigned char rtc_read (unsigned char reg);
75static void rtc_write (unsigned char reg, unsigned char val);
76
77
78
79
80
81/* ************************************************************************* */
82#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
83
84static void soft_spi_send (unsigned char n);
85static unsigned char soft_spi_read (void);
86static void init_spi (void);
wdenkaffae2b2002-08-17 09:36:01 +000087
88/*-----------------------------------------------------------------------
89 * Definitions
90 */
91
92#define PB_SPISCK 0x00000002 /* PB 30 */
93#define PB_SPIMOSI 0x00000004 /* PB 29 */
94#define PB_SPIMISO 0x00000008 /* PB 28 */
95#define PB_SPI_CE 0x00010000 /* PB 15 */
96
97/* ------------------------------------------------------------------------- */
98
99/* read clock time from DS1306 and return it in *tmp */
wdenkc0bc2e12004-02-09 23:12:24 +0000100void rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000101{
wdenkc0bc2e12004-02-09 23:12:24 +0000102 volatile immap_t *immap = (immap_t *) CFG_IMMR;
103 unsigned char spi_byte; /* Data Byte */
wdenkaffae2b2002-08-17 09:36:01 +0000104
wdenkc0bc2e12004-02-09 23:12:24 +0000105 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000106
wdenkc0bc2e12004-02-09 23:12:24 +0000107 /* Now we can enable the DS1306 RTC */
108 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
109 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000110
wdenkc0bc2e12004-02-09 23:12:24 +0000111 /* Shift out the address (0) of the time in the Clock Chip */
112 soft_spi_send (0);
wdenkaffae2b2002-08-17 09:36:01 +0000113
wdenkc0bc2e12004-02-09 23:12:24 +0000114 /* Put the clock readings into the rtc_time structure */
115 tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
116 tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
wdenkaffae2b2002-08-17 09:36:01 +0000117
wdenkc0bc2e12004-02-09 23:12:24 +0000118 /* Hours are trickier */
119 spi_byte = soft_spi_read (); /* Read Hours into temporary value */
120 if (spi_byte & 0x40) {
121 /* 12 hour mode bit is set (time is in 1-12 format) */
122 if (spi_byte & 0x20) {
123 /* since PM we add 11 to get 0-23 for hours */
124 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
125 } else {
126 /* since AM we subtract 1 to get 0-23 for hours */
127 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
128 }
129 } else {
130 /* Otherwise, 0-23 hour format */
131 tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
wdenkaffae2b2002-08-17 09:36:01 +0000132 }
wdenkaffae2b2002-08-17 09:36:01 +0000133
wdenkc0bc2e12004-02-09 23:12:24 +0000134 soft_spi_read (); /* Read and discard Day of week */
135 tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
136 tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
wdenkaffae2b2002-08-17 09:36:01 +0000137
wdenkc0bc2e12004-02-09 23:12:24 +0000138 /* Read Year and convert to this century */
139 tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
wdenkaffae2b2002-08-17 09:36:01 +0000140
wdenkc0bc2e12004-02-09 23:12:24 +0000141 /* Now we can disable the DS1306 RTC */
142 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
143 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000144
wdenkc0bc2e12004-02-09 23:12:24 +0000145 GregorianDay (tmp); /* Determine the day of week */
wdenkaffae2b2002-08-17 09:36:01 +0000146
wdenkc0bc2e12004-02-09 23:12:24 +0000147 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
148 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
149 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000150}
151
152/* ------------------------------------------------------------------------- */
153
154/* set clock time in DS1306 RTC and in MPC8xx RTC */
wdenkc0bc2e12004-02-09 23:12:24 +0000155void rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000156{
wdenkc0bc2e12004-02-09 23:12:24 +0000157 volatile immap_t *immap = (immap_t *) CFG_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000158
wdenkc0bc2e12004-02-09 23:12:24 +0000159 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000160
wdenkc0bc2e12004-02-09 23:12:24 +0000161 /* Now we can enable the DS1306 RTC */
162 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
163 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000164
wdenkc0bc2e12004-02-09 23:12:24 +0000165 /* First disable write protect in the clock chip control register */
166 soft_spi_send (0x8F); /* send address of the control register */
167 soft_spi_send (0x00); /* send control register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000168
wdenkc0bc2e12004-02-09 23:12:24 +0000169 /* Now disable the DS1306 to terminate the write */
170 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
171 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000172
wdenkc0bc2e12004-02-09 23:12:24 +0000173 /* Now enable the DS1306 to initiate a new write */
174 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
175 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000176
wdenkc0bc2e12004-02-09 23:12:24 +0000177 /* Next, send the address of the clock time write registers */
178 soft_spi_send (0x80); /* send address of the first time register */
wdenkaffae2b2002-08-17 09:36:01 +0000179
wdenkc0bc2e12004-02-09 23:12:24 +0000180 /* Use Burst Mode to send all of the time data to the clock */
181 bin2bcd (tmp->tm_sec);
182 soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
183 soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
184 soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
185 soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
186 soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
187 soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
188 soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
wdenkaffae2b2002-08-17 09:36:01 +0000189
wdenkc0bc2e12004-02-09 23:12:24 +0000190 /* Now we can disable the Clock chip to terminate the burst write */
191 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
192 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000193
wdenkc0bc2e12004-02-09 23:12:24 +0000194 /* Now we can enable the Clock chip to initiate a new write */
195 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
196 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000197
wdenkc0bc2e12004-02-09 23:12:24 +0000198 /* First we Enable write protect in the clock chip control register */
199 soft_spi_send (0x8F); /* send address of the control register */
200 soft_spi_send (0x40); /* send out Control Register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000201
wdenkc0bc2e12004-02-09 23:12:24 +0000202 /* Now disable the DS1306 */
203 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
204 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000205
wdenkc0bc2e12004-02-09 23:12:24 +0000206 /* Set standard MPC8xx clock to the same time so Linux will
207 * see the time even if it doesn't have a DS1306 clock driver.
208 * This helps with experimenting with standard kernels.
209 */
210 {
211 ulong tim;
wdenkaffae2b2002-08-17 09:36:01 +0000212
wdenkc0bc2e12004-02-09 23:12:24 +0000213 tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
214 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000215
wdenkc0bc2e12004-02-09 23:12:24 +0000216 immap->im_sitk.sitk_rtck = KAPWR_KEY;
217 immap->im_sit.sit_rtc = tim;
218 }
wdenkaffae2b2002-08-17 09:36:01 +0000219
wdenkc0bc2e12004-02-09 23:12:24 +0000220 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
221 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
222 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000223}
224
225/* ------------------------------------------------------------------------- */
226
wdenkc0bc2e12004-02-09 23:12:24 +0000227/* Initialize Port B for software SPI */
228static void init_spi (void)
wdenkaffae2b2002-08-17 09:36:01 +0000229{
wdenkc0bc2e12004-02-09 23:12:24 +0000230 volatile immap_t *immap = (immap_t *) CFG_IMMR;
231
232 /* Force output pins to begin at logic 0 */
233 immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
234
235 /* Set these 3 signals as outputs */
236 immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
237
238 immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
239 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000240}
241
242/* ------------------------------------------------------------------------- */
243
wdenkc0bc2e12004-02-09 23:12:24 +0000244/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
245static void soft_spi_send (unsigned char n)
wdenkaffae2b2002-08-17 09:36:01 +0000246{
wdenkc0bc2e12004-02-09 23:12:24 +0000247 volatile immap_t *immap = (immap_t *) CFG_IMMR;
248 unsigned char bitpos; /* bit position to receive */
249 unsigned char i; /* Loop Control */
250
251 /* bit position to send, start with most significant bit */
252 bitpos = 0x80;
253
254 /* Send 8 bits to software SPI */
255 for (i = 0; i < 8; i++) { /* Loop for 8 bits */
256 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
257
258 if (n & bitpos)
259 immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
260 else
261 immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
262 udelay (10);
263
264 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
265 udelay (10);
266
267 bitpos >>= 1; /* Shift for next bit position */
268 }
wdenkaffae2b2002-08-17 09:36:01 +0000269}
270
271/* ------------------------------------------------------------------------- */
272
wdenkc0bc2e12004-02-09 23:12:24 +0000273/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
274static unsigned char soft_spi_read (void)
wdenkaffae2b2002-08-17 09:36:01 +0000275{
wdenkc0bc2e12004-02-09 23:12:24 +0000276 volatile immap_t *immap = (immap_t *) CFG_IMMR;
277
278 unsigned char spi_byte = 0; /* Return value, assume success */
279 unsigned char bitpos; /* bit position to receive */
280 unsigned char i; /* Loop Control */
281
282 /* bit position to receive, start with most significant bit */
283 bitpos = 0x80;
284
285 /* Read 8 bits here */
286 for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
287 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
288 udelay (10);
289 if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
290 spi_byte |= bitpos; /* Set data accordingly */
291 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
292 udelay (10);
293 bitpos >>= 1; /* Shift for next bit position */
294 }
295
296 return spi_byte; /* Return the byte read */
wdenkaffae2b2002-08-17 09:36:01 +0000297}
298
299/* ------------------------------------------------------------------------- */
300
wdenkc0bc2e12004-02-09 23:12:24 +0000301void rtc_reset (void)
302{
303 return; /* nothing to do */
304}
wdenkaffae2b2002-08-17 09:36:01 +0000305
wdenkc0bc2e12004-02-09 23:12:24 +0000306#else /* not CONFIG_SXNI855T */
307/* ************************************************************************* */
wdenkaffae2b2002-08-17 09:36:01 +0000308
wdenkc0bc2e12004-02-09 23:12:24 +0000309
310
wdenkaffae2b2002-08-17 09:36:01 +0000311
wdenkc0bc2e12004-02-09 23:12:24 +0000312
313/* read clock time from DS1306 and return it in *tmp */
314void rtc_get (struct rtc_time *tmp)
315{
316 unsigned char sec, min, hour, mday, wday, mon, year;
317
318 sec = rtc_read (RTC_SECONDS);
319 min = rtc_read (RTC_MINUTES);
320 hour = rtc_read (RTC_HOURS);
321 mday = rtc_read (RTC_DATE_OF_MONTH);
322 wday = rtc_read (RTC_DAY_OF_WEEK);
323 mon = rtc_read (RTC_MONTH);
324 year = rtc_read (RTC_YEAR);
325
326 debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
327 "hr: %02x min: %02x sec: %02x\n",
328 year, mon, mday, wday, hour, min, sec);
329 debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
330 rtc_read (RTC_DAY_OF_WEEK_ALARM0),
331 rtc_read (RTC_HOURS_ALARM0),
332 rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
333 debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
334 rtc_read (RTC_DAY_OF_WEEK_ALARM1),
335 rtc_read (RTC_HOURS_ALARM1),
336 rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
337
338 tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
339 tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
340
341 /* convert Hours */
342 tmp->tm_hour = (hour & 0x40)
343 ? ((hour & 0x20) /* 12 hour mode */
344 ? bcd2bin (hour & 0x1F) + 11 /* PM */
345 : bcd2bin (hour & 0x1F) - 1 /* AM */
346 )
347 : bcd2bin (hour & 0x3F); /* 24 hour mode */
348
349 tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
350 tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
351 tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
352 tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
353 tmp->tm_yday = 0;
354 tmp->tm_isdst = 0;
355
356 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
357 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
358 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000359}
360
361/* ------------------------------------------------------------------------- */
362
wdenkc0bc2e12004-02-09 23:12:24 +0000363/* set clock time from *tmp in DS1306 RTC */
364void rtc_set (struct rtc_time *tmp)
365{
366 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
367 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
368 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
369
370 rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
371 rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
372 rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
373 rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
374 rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
375 rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
376 rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
377}
378
379/* ------------------------------------------------------------------------- */
380
381/* reset the DS1306 */
382void rtc_reset (void)
wdenkaffae2b2002-08-17 09:36:01 +0000383{
wdenkc0bc2e12004-02-09 23:12:24 +0000384 /* clear the control register */
385 rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
386 rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
wdenkaffae2b2002-08-17 09:36:01 +0000387
wdenkc0bc2e12004-02-09 23:12:24 +0000388 /* reset all alarms */
389 rtc_write (RTC_SECONDS_ALARM0, 0x00);
390 rtc_write (RTC_SECONDS_ALARM1, 0x00);
391 rtc_write (RTC_MINUTES_ALARM0, 0x00);
392 rtc_write (RTC_MINUTES_ALARM1, 0x00);
393 rtc_write (RTC_HOURS_ALARM0, 0x00);
394 rtc_write (RTC_HOURS_ALARM1, 0x00);
395 rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
396 rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
397}
wdenkaffae2b2002-08-17 09:36:01 +0000398
wdenkc0bc2e12004-02-09 23:12:24 +0000399/* ------------------------------------------------------------------------- */
wdenkaffae2b2002-08-17 09:36:01 +0000400
wdenkc0bc2e12004-02-09 23:12:24 +0000401static unsigned char rtc_read (unsigned char reg)
402{
403 unsigned char dout[2]; /* SPI Output Data Bytes */
404 unsigned char din[2]; /* SPI Input Data Bytes */
wdenkaffae2b2002-08-17 09:36:01 +0000405
wdenkc0bc2e12004-02-09 23:12:24 +0000406 dout[0] = reg;
wdenkaffae2b2002-08-17 09:36:01 +0000407
wdenkc0bc2e12004-02-09 23:12:24 +0000408 if (spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din) != 0) {
409 return 0;
410 } else {
411 return din[1];
412 }
wdenkaffae2b2002-08-17 09:36:01 +0000413}
414
415/* ------------------------------------------------------------------------- */
416
wdenkc0bc2e12004-02-09 23:12:24 +0000417static void rtc_write (unsigned char reg, unsigned char val)
wdenkaffae2b2002-08-17 09:36:01 +0000418{
wdenkc0bc2e12004-02-09 23:12:24 +0000419 unsigned char dout[2]; /* SPI Output Data Bytes */
420 unsigned char din[2]; /* SPI Input Data Bytes */
wdenkaffae2b2002-08-17 09:36:01 +0000421
wdenkc0bc2e12004-02-09 23:12:24 +0000422 dout[0] = 0x80 | reg;
423 dout[1] = val;
wdenkaffae2b2002-08-17 09:36:01 +0000424
wdenkc0bc2e12004-02-09 23:12:24 +0000425 spi_xfer (spi_chipsel[CFG_SPI_RTC_DEVID], 16, dout, din);
426}
427
428#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
wdenkaffae2b2002-08-17 09:36:01 +0000429
wdenkc0bc2e12004-02-09 23:12:24 +0000430/* ------------------------------------------------------------------------- */
wdenkaffae2b2002-08-17 09:36:01 +0000431
wdenkc0bc2e12004-02-09 23:12:24 +0000432static unsigned char bcd2bin (unsigned char n)
433{
434 return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
wdenkaffae2b2002-08-17 09:36:01 +0000435}
436
437/* ------------------------------------------------------------------------- */
438
wdenkc0bc2e12004-02-09 23:12:24 +0000439static unsigned int bin2bcd (unsigned int n)
440{
441 return (((n / 10) << 4) | (n % 10));
442}
443/* ------------------------------------------------------------------------- */
444
wdenkaffae2b2002-08-17 09:36:01 +0000445#endif