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git01.mediatek.com / filogic / uboot / db84b5691dbf497bfd7a60b23940c8b43350e9e9 / . / board / d-link / dns325 / dns325.c
blob: 0ae2e7d88c106ddd41e710f9c314b8215240f6e7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]2/*
3 * Copyright (C) 2011
Stefan Herbrechtsmeier91eafc02014-12-28 14:09:50 +0100[diff] [blame]4 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]10 */
11
12#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]13#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]14#include <log.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]15#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]16#include <net.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]17#include <netdev.h>
18#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]19#include <asm/arch/soc.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]20#include <asm/arch/mpp.h>
21#include <asm/arch/gpio.h>
22#include "dns325.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26int board_early_init_f(void)
27{
28 /* Gpio configuration */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]29 mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
30 DNS325_OE_LOW, DNS325_OE_HIGH);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]31
32 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]33 static const u32 kwmpp_config[] = {
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]34 MPP0_NF_IO2,
35 MPP1_NF_IO3,
36 MPP2_NF_IO4,
37 MPP3_NF_IO5,
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_TW_SDA,
43 MPP9_TW_SCK,
44 MPP10_UART0_TXD,
45 MPP11_UART0_RXD,
46 MPP12_SD_CLK,
47 MPP13_SD_CMD,
48 MPP14_SD_D0,
49 MPP15_SD_D1,
50 MPP16_SD_D2,
51 MPP17_SD_D3,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP20_SATA1_ACTn, /* sata1(left) status led */
55 MPP21_SATA0_ACTn, /* sata0(right) status led */
56 MPP22_GPIO,
57 MPP23_GPIO,
58 MPP24_GPIO, /* power off out */
59 MPP25_GPIO,
60 MPP26_GPIO, /* power led */
61 MPP27_GPIO, /* sata0(right) error led */
62 MPP28_GPIO, /* sata1(left) error led */
63 MPP29_GPIO, /* usb error led */
64 MPP30_GPIO,
65 MPP31_GPIO,
66 MPP32_GPIO,
67 MPP33_GPIO,
68 MPP34_GPIO, /* power key */
69 MPP35_GPIO,
70 MPP36_GPIO,
71 MPP37_GPIO,
72 MPP38_GPIO,
73 MPP39_GPIO, /* enable sata 0 */
74 MPP40_GPIO, /* enable sata 1 */
75 MPP41_GPIO, /* hdd0 present */
76 MPP42_GPIO, /* hdd1 present */
77 MPP43_GPIO, /* usb status led */
78 MPP44_GPIO, /* fan status */
79 MPP45_GPIO, /* fan high speed */
80 MPP46_GPIO, /* fan low speed */
81 MPP47_GPIO, /* usb umount */
82 MPP48_GPIO, /* factory reset */
83 MPP49_GPIO, /* thermal sensor */
84 0
85 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]86 kirkwood_mpp_conf(kwmpp_config, NULL);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]87
88 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
89
90 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
91 return 0;
92}
93
94int board_init(void)
95{
96 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]97 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]98
99 return 0;
100}
101
102#ifdef CONFIG_RESET_PHY_R
103/* Configure and initialize PHY */
104void reset_phy(void)
105{
106 u16 reg;
107 u16 devadr;
108 char *name = "egiga0";
109
110 if (miiphy_set_current_dev(name))
111 return;
112
113 /* command to read PHY dev address */
114 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
115 printf("Err..(%s) could not read PHY dev address\n", __func__);
116 return;
117 }
118
119 /*
120 * Enable RGMII delay on Tx and Rx for CPU port
121 * Ref: sec 4.7.2 of chip datasheet
122 */
123 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
124 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
125 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
126 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
127 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
128
129 /* reset the phy */
130 miiphy_reset(name, devadr);
131
132 debug("88E1116 Initialized on %s\n", name);
133}
134#endif /* CONFIG_RESET_PHY_R */