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git01.mediatek.com / filogic / uboot / 97589738436d014a2d1e5bf6df055df6c96a8ae8 / . / board / d-link / dns325 / dns325.c
blob: a0f3dada42ccb80787c94c2ece48bf2e588c2111 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]2/*
3 * Copyright (C) 2011
Stefan Herbrechtsmeier91eafc02014-12-28 14:09:50 +0100[diff] [blame]4 * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]10 */
11
12#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame^]13#include <init.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]14#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]15#include <net.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]16#include <netdev.h>
17#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]18#include <asm/arch/soc.h>
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]19#include <asm/arch/mpp.h>
20#include <asm/arch/gpio.h>
21#include "dns325.h"
22
23DECLARE_GLOBAL_DATA_PTR;
24
25int board_early_init_f(void)
26{
27 /* Gpio configuration */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]28 mvebu_config_gpio(DNS325_OE_VAL_LOW, DNS325_OE_VAL_HIGH,
29 DNS325_OE_LOW, DNS325_OE_HIGH);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]30
31 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]32 static const u32 kwmpp_config[] = {
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]33 MPP0_NF_IO2,
34 MPP1_NF_IO3,
35 MPP2_NF_IO4,
36 MPP3_NF_IO5,
37 MPP4_NF_IO6,
38 MPP5_NF_IO7,
39 MPP6_SYSRST_OUTn,
40 MPP7_GPO,
41 MPP8_TW_SDA,
42 MPP9_TW_SCK,
43 MPP10_UART0_TXD,
44 MPP11_UART0_RXD,
45 MPP12_SD_CLK,
46 MPP13_SD_CMD,
47 MPP14_SD_D0,
48 MPP15_SD_D1,
49 MPP16_SD_D2,
50 MPP17_SD_D3,
51 MPP18_NF_IO0,
52 MPP19_NF_IO1,
53 MPP20_SATA1_ACTn, /* sata1(left) status led */
54 MPP21_SATA0_ACTn, /* sata0(right) status led */
55 MPP22_GPIO,
56 MPP23_GPIO,
57 MPP24_GPIO, /* power off out */
58 MPP25_GPIO,
59 MPP26_GPIO, /* power led */
60 MPP27_GPIO, /* sata0(right) error led */
61 MPP28_GPIO, /* sata1(left) error led */
62 MPP29_GPIO, /* usb error led */
63 MPP30_GPIO,
64 MPP31_GPIO,
65 MPP32_GPIO,
66 MPP33_GPIO,
67 MPP34_GPIO, /* power key */
68 MPP35_GPIO,
69 MPP36_GPIO,
70 MPP37_GPIO,
71 MPP38_GPIO,
72 MPP39_GPIO, /* enable sata 0 */
73 MPP40_GPIO, /* enable sata 1 */
74 MPP41_GPIO, /* hdd0 present */
75 MPP42_GPIO, /* hdd1 present */
76 MPP43_GPIO, /* usb status led */
77 MPP44_GPIO, /* fan status */
78 MPP45_GPIO, /* fan high speed */
79 MPP46_GPIO, /* fan low speed */
80 MPP47_GPIO, /* usb umount */
81 MPP48_GPIO, /* factory reset */
82 MPP49_GPIO, /* thermal sensor */
83 0
84 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]85 kirkwood_mpp_conf(kwmpp_config, NULL);
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]86
87 kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1);
88
89 kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1);
90 return 0;
91}
92
93int board_init(void)
94{
95 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]96 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Stefanc98efc32011-12-23 06:35:04 +0000[diff] [blame]97
98 return 0;
99}
100
101#ifdef CONFIG_RESET_PHY_R
102/* Configure and initialize PHY */
103void reset_phy(void)
104{
105 u16 reg;
106 u16 devadr;
107 char *name = "egiga0";
108
109 if (miiphy_set_current_dev(name))
110 return;
111
112 /* command to read PHY dev address */
113 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
114 printf("Err..(%s) could not read PHY dev address\n", __func__);
115 return;
116 }
117
118 /*
119 * Enable RGMII delay on Tx and Rx for CPU port
120 * Ref: sec 4.7.2 of chip datasheet
121 */
122 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
123 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
124 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
125 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
126 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
127
128 /* reset the phy */
129 miiphy_reset(name, devadr);
130
131 debug("88E1116 Initialized on %s\n", name);
132}
133#endif /* CONFIG_RESET_PHY_R */