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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutad43cd32017-07-21 23:15:21 +02002/*
3 * board/renesas/ulcb/ulcb.c
4 * This file is ULCB board support.
5 *
6 * Copyright (C) 2017 Renesas Electronics Corporation
Marek Vasutad43cd32017-07-21 23:15:21 +02007 */
8
9#include <common.h>
10#include <malloc.h>
11#include <netdev.h>
12#include <dm.h>
13#include <dm/platform_data/serial_sh.h>
14#include <asm/processor.h>
15#include <asm/mach-types.h>
16#include <asm/io.h>
17#include <linux/errno.h>
18#include <asm/arch/sys_proto.h>
19#include <asm/gpio.h>
20#include <asm/arch/gpio.h>
21#include <asm/arch/rmobile.h>
22#include <asm/arch/rcar-mstp.h>
23#include <asm/arch/sh_sdhi.h>
24#include <i2c.h>
25#include <mmc.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29#define CPGWPCR 0xE6150904
30#define CPGWPR 0xE615090C
31
32#define CLK2MHZ(clk) (clk / 1000 / 1000)
33void s_init(void)
34{
35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
37
38 /* Watchdog init */
39 writel(0xA5A5A500, &rwdt->rwtcsra);
40 writel(0xA5A5A500, &swdt->swtcsra);
41
42 writel(0xA5A50000, CPGWPCR);
43 writel(0xFFFFFFFF, CPGWPR);
44}
45
46#define GSX_MSTP112 BIT(12) /* 3DG */
47#define TMU0_MSTP125 BIT(25) /* secure */
48#define TMU1_MSTP124 BIT(24) /* non-secure */
49#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
Marek Vasutad43cd32017-07-21 23:15:21 +020050#define DVFS_MSTP926 BIT(26)
Marek Vasutcea5c8f2017-09-12 19:07:22 +020051#define HSUSB_MSTP704 BIT(4) /* HSUSB */
Marek Vasutad43cd32017-07-21 23:15:21 +020052
Marek Vasutad43cd32017-07-21 23:15:21 +020053int board_early_init_f(void)
54{
55 /* TMU0,1 */ /* which use ? */
56 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
Marek Vasutad43cd32017-07-21 23:15:21 +020057
58#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
59 /* DVFS for reset */
60 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
61#endif
62 return 0;
63}
64
65/* SYSC */
66/* R/- 32 Power status register 2(3DG) */
67#define SYSC_PWRSR2 0xE6180100
68/* -/W 32 Power resume control register 2 (3DG) */
69#define SYSC_PWRONCR2 0xE618010C
70
Marek Vasutcea5c8f2017-09-12 19:07:22 +020071/* HSUSB block registers */
72#define HSUSB_REG_LPSTS 0xE6590102
73#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
74#define HSUSB_REG_UGCTRL2 0xE6590184
75#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
76#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
77
Marek Vasutad43cd32017-07-21 23:15:21 +020078int board_init(void)
79{
80 /* adress of boot parameters */
81 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
82
Marek Vasutad43cd32017-07-21 23:15:21 +020083 /* USB1 pull-up */
84 setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
85
Marek Vasutcea5c8f2017-09-12 19:07:22 +020086 /* Configure the HSUSB block */
87 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
88 /* Choice USB0SEL */
89 clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
90 HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
91 /* low power status */
92 setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
93
Marek Vasut7cf1c7f2017-08-20 17:13:48 +020094 return 0;
Marek Vasutad43cd32017-07-21 23:15:21 +020095}
Marek Vasutad43cd32017-07-21 23:15:21 +020096
97int dram_init(void)
98{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053099 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasut1c7ad492017-11-27 05:37:53 +0100100 return -EINVAL;
Marek Vasutad43cd32017-07-21 23:15:21 +0200101
102 return 0;
103}
104
105int dram_init_banksize(void)
106{
Marek Vasut1c7ad492017-11-27 05:37:53 +0100107 fdtdec_setup_memory_banksize();
108
Marek Vasutad43cd32017-07-21 23:15:21 +0200109 return 0;
110}