| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 2 | /* |
| 3 | * SoC-specific setup info |
| 4 | * |
| 5 | * (C) Copyright 2010,2011 |
| 6 | * NVIDIA Corporation <www.nvidia.com> |
| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 10 | #include <linux/linkage.h> |
| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 11 | |
| Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 12 | #ifdef CONFIG_ARM64 |
| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 13 | .align 5 |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 14 | ENTRY(reset_cpu) |
| Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 15 | /* get address for global reset register */ |
| 16 | ldr x1, =PRM_RSTCTRL |
| 17 | ldr w3, [x1] |
| 18 | /* force reset */ |
| 19 | orr w3, w3, #0x10 |
| 20 | str w3, [x1] |
| 21 | mov w0, w0 |
| 22 | 1: |
| 23 | b 1b |
| 24 | ENDPROC(reset_cpu) |
| 25 | #else |
| 26 | .align 5 |
| 27 | ENTRY(reset_cpu) |
| Tom Warren | 41b6838 | 2011-01-27 10:58:05 +0000 | [diff] [blame] | 28 | ldr r1, rstctl @ get addr for global reset |
| 29 | @ reg |
| 30 | ldr r3, [r1] |
| 31 | orr r3, r3, #0x10 |
| 32 | str r3, [r1] @ force reset |
| 33 | mov r0, r0 |
| 34 | _loop_forever: |
| 35 | b _loop_forever |
| 36 | rstctl: |
| 37 | .word PRM_RSTCTRL |
| Aneesh V | fd8798b | 2012-03-08 07:20:18 +0000 | [diff] [blame] | 38 | ENDPROC(reset_cpu) |
| Tom Warren | ab0cc6b | 2015-03-04 16:36:00 -0700 | [diff] [blame] | 39 | #endif |